ST93C06
ST93C06C
256 bit (16 x 16 or 32 x 8) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
DUAL ORGANIZATION: 16 x 16 or 32 x 8
BYTE/WORD and ENTIRE MEMORY
PROGRAMMING INSTRUCTIONS
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE
READY/BUSY SIGNAL DURING
PROGRAMMING
SINGLE 5V
±10%
SUPPLY VOLTAGE
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
ENHANCED ESD/LATCH UP
PERFORMANCES for ”C” VERSION
ST93C06 and ST93C06C are replaced by
the M93C06
DESCRIPTION
The ST93C06 and ST93C06C are 256 bit Electri-
cally Erasable Programmable Memory (EEPROM)
fabricated with SGS-THOMSON’s High Endurance
Single Polysilicon CMOS technology. In the text the
two products are referred to as ST93C06.
The memory is divided into either 32 x 8 bit bytes
or 16 x 16 bit words. The organization may be
selected by a signal applied on the ORG input.
The memory is accessed through a serial input (D)
and by a set of instructions which includes Read a
byte/word, Write a byte/word, Erase a byte/word,
Erase All and Write All. ARead instruction loads the
address of the first byte/word to be read into an
internal address pointer.
Table 1. Signal Names
S
D
Q
C
ORG
V
CC
V
SS
June 1997
Chip Select Input
Serial Data Input
Serial Data Output
Serial Clock
Organisation Select
Supply Voltage
Ground
8
1
PSDIP8 (B)
0.4mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
VCC
D
C
S
ORG
ST93C06
ST93C06C
Q
VSS
AI00816B
1/15
This is information on a product still in production bu t not recommended for new de signs.
ST93C06, ST93C06C
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST93C06
ST93C06C
S
C
D
Q
1
2
3
4
8
7
6
5
AI00817B
ST93C06
ST93C06C
VCC
DU
ORG
VSS
S
C
D
Q
1
2
3
4
8
7
6
5
AI00818C
VCC
DU
ORG
VSS
Warning:
DU = Don’t Use
Warning:
DU = Don’t Use
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
STG
T
LEAD
V
IO
V
CC
Parameter
Ambient Operating Temperature
Storage Temperature
Lead Temperature, Soldering
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
Value
–40 to 125
–65 to 150
215
260
–0.3 to V
CC
+0.5
–0.3 to 6.5
(2)
Unit
°C
°C
°C
V
V
V
V
Input or Output Voltages (Q = V
OH
or Hi-Z)
Supply Voltage
Electrostatic Discharge Voltage (Human Body model)
ST93C06
ST93C06C
ST93C06
ST93C06C
V
ESD
Electrostatic Discharge Voltage (Machine model)
(3)
2000
4000
500
500
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500
Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0
Ω).
DESCRIPTION
(cont’d)
The data contained at this address is then clocked
out serially. The address pointer is automatically
incremented after the data is output and, if the Chip
Select input (S) is held High, the ST93C06 can
output a sequential stream of data bytes/words. In
this way, the memory can be read as a data stream
from 8 to 256 bits long, or continuously as the
address counter automatically rolls over to ’00’
when the highest address is reached. Program-
ming is internally self-timed (the external clock
2/15
signal on C input may be disconnected or left
running after the start of a Write cycle) and does
not require an erase cycle prior to the Write instruc-
tion. The Write instruction writes 8 or 16 bits at one
time into one of the 32 bytes or 16 words. After the
start of the programming cycle aBusy/Ready signal
is available on the Data output (Q) when Chip
Select (S) is driven High.
The design of the ST93C06 and the High Endur-
ance CMOS technologyused for its fabrication give
an Erase/Write cycle Endurance of 1,000,000 cy-
cles and a data retention of 40 years.
ST93C06, ST93C06C
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Input Timing Reference Voltages
Output Timing Reference Voltages
≤
20ns
0.4V to 2.4V
1V to 2.0V
0.8V to 2.0V
Figure 3. AC Testing Input Output Waveforms
2.4V
2V
1V
2.0V
0.8V
OUTPUT
AI00815
0.4V
Note that Output Hi-Z is defined as the point where data
is no longer driven.
INPUT
Table 3. Capacitance
(1)
(T
A
= 25
°C,
f = 1 MHz )
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min
Max
5
5
Unit
pF
pF
Note:
1. Sampled only, not 100% tested.
Table 4. DC Characteristics
(T
A
= 0 to 70°C or –40 to 85°C; V
CC
= 5V
±
10%)
Symbol
I
LI
I
LO
I
CC
Parameter
Input Leakage Current
Output Leakage Current
Supply Current (TTL Inputs)
Supply Current (CMOS Inputs)
I
CC1
V
IL
V
IH
V
OL
Supply Current (Standby)
Input Low Voltage (D, C, S)
Input High Voltage (D, C, S)
Output Low Voltage
I
OL
= 2.1mA
I
OL
= 10
µA
I
OH
= –400µA
I
OH
= –10µA
2.4
V
CC
– 0.2
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
,
Q in Hi-Z
S = V
IH
, f = 1 MHz
S = V
IH
, f = 1 MHz
S = V
SS
, C = V
SS
,
ORG = V
SS
or V
CC
–0.3
2
Min
Max
±2.5
±2.5
3
2
50
0.8
V
CC
+ 1
0.4
0.2
Unit
µA
µA
mA
mA
µA
V
V
V
V
V
V
V
OH
Output High Voltage
3/15
ST93C06, ST93C06C
Table 5. AC Characteristics
(T
A
= 0 to 70°C or –40 to 85°C; V
CC
= 5V
±
10%)
Symbol
t
SHCH
t
CLSH
t
DVCH
t
CHDX
Alt
t
CSS
t
SKS
t
DIS
t
DIH
Parameter
Chip Select High to Clock High
Clock Low to Chip Select High
Input Valid to Clock High
Temp. Range: grade 1
Clock High to Input Transition
Temp. Range:
grades 3, 6
Test Condition
Min
50
100
100
100
200
500
500
0
250
Note 1
250
500
ST93C06
ST93C06C
t
CHCL
t
CLCH
t
W
f
C
t
SKH
t
SKL
t
WP
f
SK
Clock High to Clock Low
Clock Low to Clock High
Erase/Write Cycle time
Clock Frequency
0
Note 2
Note 2
250
250
10
1
300
200
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
MHz
t
CHQL
t
CHQV
t
CLSL
t
SLCH
t
SLSH
t
SHQV
t
SLQZ
t
PD0
t
PD1
t
CSH
Clock High to Output Low
Clock High to Output Valid
Clock Low to Chip Select Low
Chip Select Low to Clock High
t
CS
t
SV
t
DF
Chip Select Low to Chip Select High
Chip Select High to Output Valid
Chip Select Low to Output Hi-Z
Notes:
1. Chip Select must be brought low for a minimum of 250 ns (t
SLSH
) between consecutive instruction cycles.
2. The Clock frequency specification calls for a minimum clock period of 1
µs,
therefore the sum of the timings t
CHCL
+ t
CLCH
must be greater or equal to 1
µs.
For example, if t
CHCL
is 250 ns, then t
CLCH
must be at least 750 ns.
Figure 4. Synchronous Timing, Start and Op-Code Input
tCLSH
C
tSHCH
S
tDVCH
D
START
OP CODE
tCHCL
tCLCH
tCHDX
OP CODE
OP CODE
OP CODE
START
OP CODE INPUT
AI00819C
4/15
ST93C06, ST93C06C
Figure 5. Synchronous Timing, Read or Write
C
tCLSL
S
tDVCH
D
An
tCHQL
Q15/Q7
tCHDX
A0
tSLQZ
Q0
tCHQV
tSLSH
Hi-Z
Q
ADDRESS INPUT
DATA OUTPUT
AI00820C
tSLCH
C
tCLSL
S
tDVCH
D
An
tCHDX
A0/D0
tSHQV
Hi-Z
Q
BUSY
tW
ADDRESS/DATA INPUT
WRITE CYCLE
AI01429
tSLSH
tSLQZ
READY
DESCRIPTION
(cont’d)
The DU (Don’t Use) pin does not affect the function
of the memory and it is reserved for use by SGS-
THOMSON during test sequences.The pin may be
left unconnected or may be connected to V
CC
or
V
SS
. Direct connection of DU to V
SS
is recom-
mended for the lowest standby power consump-
tion.
MEMORY ORGANIZATION
The ST93C06 is organized as 32 bytes x 8 bits or
16 words x 16 bits. If the ORG input is left uncon-
nected (or connected to V
CC
) the x16 organization
is selected, when ORG is connected to Ground
(V
SS
) the x8 organization is selected. When the
ST93C06 is in standby mode, the ORG input
should be unconnected or set to either V
SS
or V
CC
in order to achieve the minimum power consump-
tion. Any voltage between V
SS
and V
CC
applied to
ORG may increase the standby current value.
5/15
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