ST95040
ST95020, ST95010
4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE
– 4.5V to 5.5V for ST950x0
– 2.5V to 5.5V for ST950x0W
SPI BUS COMPATIBLE SERIAL INTERFACE
2 MHz CLOCK RATE MAX
BLOCK WRITE PROTECTION
STATUS REGISTER
16 BYTE PAGE MODE
WRITE PROTECT
SELF-TIMED PROGRAMMING CYCLE
E.S.D.PROTECTION GREATER than 4000V
SUPPORTS POSITIVE CLOCK SPI MODES
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
The ST950x0 is a family of Electrically Erasable
Programmable Memories (EEPROM) fabricated
with STMicroelectronics’s High Endurance Single
Polysilicon CMOS technology. Each memory is
accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q).
VCC
D
C
Q
Table 1. Signal Names
C
D
Q
S
W
HOLD
V
CC
V
SS
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
Supply Voltage
Ground
S
W
HOLD
ST950x0
VSS
AI01435B
June 1998
1/18
ST95040, ST95020, ST95010
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST950x0
S
Q
W
VSS
1
2
3
4
8
7
6
5
AI01436B
ST950x0
VCC
HOLD
C
D
S
Q
W
VSS
1
2
3
4
8
7
6
5
AI01437B
VCC
HOLD
C
D
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
STG
T
LEAD
V
O
V
I
V
CC
V
ESD
Parameter
Ambient Operating Temperature
Storage Temperature
Lead Temperature, Soldering
Output Voltage
Input Voltage with respect to Ground
Supply Voltage
Electrostatic Discharge Voltage (Human Body model)
(2)
Electrostatic Discharge Voltage (Machine model)
(3)
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
Value
–40 to 125
–65 to 150
215
260
–0.3 to V
CC
+0.6
–0.3 to 6.5
–0.3 to 6.5
4000
500
Unit
°C
°
C
°
C
V
V
V
V
V
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500Ω)
3. EIAJ IC-121 (Condition C) (200pF, 0Ω)
DESCRIPTION
(cont’d)
The device connected to the bus is selected when
the chip select input (S) goes low. Communications
with the chip can be interrupted with a hold input
(HOLD). The write operation is disabled by a write
protect input (W).
Data is clocked in during the low to high transition
of clock C, data is clocked out during the high to
low transition of clock C.
SIGNALS DESCRIPTION
Serial Output (Q).
The output pin is used to trans-
fer data serially out of the Memory. Data is shifted
out on the falling edge of the serial clock.
Serial Input (D).
The input pin is used to transfer
data serially into the device. It receivesinstructions,
addresses, and the data to be written. Input is
latched on the rising edge of the serial clock.
2/18
ST95040, ST95020, ST95010
Figure 3. Data and Clock Timing
CPOL
CPHA
0
0
C
1
1
C
D or Q
MSB
LSB
AI01438
Figure 4. Microcontroller and SPI Interface Set-up
MICROCONTROLLER
(ST6, ST7, ST9, ST10, OTHERS)
SCK
SPI Interface with
(CPOL, CPHA) =
(’0’, ’0’) or (’1’, ’1’)
SDI
SDO
C
Q
D
ST95xx0
AI01439B
Serial Clock (C).
The serial clock provides the
timing of the serial interface. Instructions, ad-
dresses, or data present at the input pin are latched
on the rising edge of the clock input, while data on
the Q pin changes after the falling edge of the clock
input.
Chip Select (S).
When S is high, the Memory is
deselected and the Q output pin is at high imped-
ance and, unless an internal write operation is
underway the Memory will be in the standby power
mode. S low enables the Memory, placing it in the
active power mode. It should be noted that after
power-on, a high to low transition on S is required
prior to the start of any operation.
Write Protect (W).
This pin is for hardware write
protection. When W is low, writes to the Memory
are disabled but any other operationsstay enabled.
When W is high, all writes operationsare available.
W going low at any time before the last bit D0 of
the data streamwill reset the write enable latch and
prevent programming. No action on W or on the
write enable latch can interrupt a write cycle which
has commenced.
3/18
ST95040, ST95020, ST95010
Hold (HOLD).
The HOLD pin is used to pause
serial communications with the Memory without
resetting the serial sequence. To take the Hold
condition into account, the product must be se-
lected (S = 0). Then the Hold state is validated by
a high to low transition on HOLD when C is low. To
resumethe communications,HOLDis broughthigh
while C is low. During the Hold condition D, Q, and
C are at a high impedance state.
When the Memory is under the Hold condition, it is
possibleto deselect the device. However, the serial
communications will remain paused after a rese-
lect, and the chip will be reset.
TheMemorycan bedrivenby a microcontroller with
its SPI peripheral running in either of the two fol-
lowing modes: (CPOL, CPHA) = (’0’, ’0’) or (CPOL,
CPHA) = (’1’, ’1’).
For these two modes, input data is latchedin by the
low to high transition of clock C, and output data is
available from the high to low transition of Clock
(C).
The differencebetween (CPOL, CPHA)= (0, 0) and
(CPOL, CPHA) = (1, 1) is the stand-by polarity: C
remains at ’0’ for (CPOL, CPHA) = (0, 0) and C
remains at ’1’for (CPOL, CPHA) = (1, 1) when there
is no data transfer.
OPERATIONS
All instructions, addresses and data are shifted in
and out of the chip MSB first. Data input (D) is
sampled on the first rising edge of clock (C) after
the chip select (S) goes low. Prior to any operation,
a one-byte instruction code must be entered in the
chip. This code is entered via the data input (D),
and latched on the rising edge of the clock input
(C). To enter an instruction code, the product must
have been previously selected (S = low). Table 3
shows the instruction set and format for device
Table 3. Instruction Set
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Description
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
Instruction Format
0000 0110
0000 0100
0000 0101
0000 0001
0000 A
8
011
0000 A
8
010
operation. If an invalid instruction is sent (one not
contained in Table 3), the chip is automatically
deselected. For operations that read or write data
in the memory array, bit 3 of the instruction is the
MSB of the address, otherwise, it is a don’t care.
Write Enable (WREN) and Write Disable (WRDI)
The Memory contains a write enable latch. This
latch must be set prior to every WRITE or WRSR
operation. The WREN instruction will set the latch
and the WRDI instruction will reset the latch. The
latch is reset under the following conditions:
– W pin is low
– Power on
– WRDI instruction executed
– WRSR instruction executed
– WRITE instruction executed
As soon as the WREN or WRDI instruction is
received by the memory, the circuit executes the
instruction and enters a wait mode until it is dese-
lected.
Read Status Register (RDSR)
TheRDSR instructionprovidesaccessto the status
register. The status register may be read at any
time, even during a write to the memory operation.
If a Read Status register reaches the 8th bit of the
Status register, an additional 9th clock pulse will
wrap around to read the 1st bit of the Status Reg-
ister
The status register format is as follows:
b7
1
1
1
1
BP1
BP0
WEL
b0
WIP
BP1, BP0: Read and write bits
WEL, WIP: Read only bits.
b7 to b4: Read only bits.
Notes:
A
8
= 1, Upper page selected on ST95040.
A
8
= 0, Lower page selected on ST95040.
4/18
ST95040, ST95020, ST95010
Figure 5. Block Diagram
HOLD
W
S
C
D
Q
Control Logic
High Voltage
Generator
I/O Shift Register
Address Register
and Counter
Data
Register
Status
Block
Protect
Y Decoder
16 Bytes
X Decoder
AI01272
During a write to the memory operation to the
memory array, all bits BP1, BP0, WEL, WIP are
valid and can be read. During a write to the status
register, only the bits WEL and WIP are valid and
can be read. The values of BP1 and BP0 read at
that time correspondto the previouscontents of the
status register.
The Write-In-Process (WIP) read-only bit indicates
whether the Memory is busy with a write operation.
When set to a ’1’ a write is in progress, when set to
a ’0’ no write is in progress.
The Write Enable Latch (WEL) read-only bit indi-
cates the status of the write enable latch. When set
to a ’1’ the latch is set, when set to a ’0’ the latch is
reset. The Block Protect (BP0 and BP1) bits indi-
cate the extent of the protection employed. These
bits are set by the user issuing the WRSR instruc-
tion. These bits are non-volatile.
5/18
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
