®
STA014 STA014B STA014T
MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM AND
SRS WOW
®
POSTPROCESSING CAPABILITY
PRODUCT PREVIEW
The Device incorporates the SRS
WOW
®
Technology under li-
cence from SRS Labs, Inc.
SINGLE CHIP MPEG2 LAYER 3 DECODER
SUPPORTING:
- All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio)
- All features specified for Layer III in ISO/IEC
13818-3.2 (MPEG 2 Audio)
- Lower sampling frequencies syntax extension,
(not specified by ISO) called MPEG 2.5
DECODES LAYER III STEREO CHANNELS,
DUAL
CHANNEL,
SINGLE
CHANNEL
(MONO)
SUPPORTING ALL THE MPEG 1 & 2 SAM-
PLING FREQUENCIES AND THE EXTEN-
SION TO MPEG 2.5:
48, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz
ACCEPTS MPEG 2.5 LAYER III ELEMEN-
TARY COMPRESSED BITSTREAM WITH
DATA RATE FROM 8 Kbit/s UP TO 320 Kbit/s
ADPCM CODEC CAPABILITIES:
- sample frequency from 8 kHz to 32 kHz
- sample size from 8 bits to 32 bits
- encoding algorithm: DVI,
ITU-G726 pack (G723-24, G721,G723-40)
- Tone control and fast-forward capability
SRS WOW
(1)
TECHNOLOGY CAN BE USED
AS POSTPROCESSING. SUPPORT FOR
DIFFERENT SPEAKERS TYPES:
- headphone
- medium
- large
WOW
(1)
TRUEBASS AND FOCUS CAN BE
INDIPENDENTLY ADJUSTED
EASY PROGRAMMABLE GPSO INTERFACE
FOR ENCODED DATA UP TO 5Mbit/s
(TQFP44 & LFBGA 64)
DIGITAL VOLUME
BASS & TREBLE CONTROL
SERIAL BITSTREAM INPUT INTERFACE
EASY PROGRAMMABLE ADC INPUT INTERFACE
ANCILLARY DATA EXTRACTION VIA I2C IN-
TERFACE.
SERIAL PCM OUTPUT INTERFACE (I
2
S
AND OTHER FORMATS)
ORDERING NUMBERS:
STA014 (SO28)
STA014T (TQFP44)
STA014B (LFBGA 64)
PLL FOR INTERNAL CLOCK AND FOR OUT-
PUT PCM CLOCK GENERATION
CRC CHECK AND SYNCHRONISATION ER-
ROR DETECTION WITH SOFTWARE INDI-
CATORS
I
2
C CONTROL BUS
LOW POWER 2.4V CMOS TECHNOLOGY
WIDE RANGE OF EXTERNAL CRYSTALS
FREQUENCIES SUPPORTED
APPLICATIONS
PC SOUND CARDS
MULTIMEDIA PLAYERS
VOICE RECORDERS
DESCRIPTION
The STA014 is a fully integrated high flexibility
MPEG Layer III Audio Decoder, capable of de-
coding Layer III compressed elementary streams,
as specified in MPEG 1 and MPEG 2 ISO stand-
ards. The device decodes also elementary streams
compressed by using low sampling rates, as speci-
fied by MPEG 2.5. STA014 receives the input data
through a Serial Input Interface. The decoded sig-
nal is a stereo, mono, or dual channel digital output
that can be sent directly to a D/A converter, by the
PCM Output Interface. This interface is software
programmable to adapt the STA014 digital output
to the most common DACs architectures used on
the market. The functional STA014 chip partitioning
is described in Fig.1a and Fig.1b.
1/45
July 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
(1)
in order to enable SRS WOW algorithm a mandatory configuration file is required.
STA014-STA014B-STA014T
1. OVERVIEW
1.1 - MP3 decoder engine
The MP3 decoder engine is able to decode any
Layer III compliant bitstream: MPEG1, MPEG2
and MPEG2.5 streams are supported. Besides
audio data decoding the MP3 engine also per-
forms ANCILLARY data extraction: these data
can be retrieved via I2C bus by the application
microcontroller in order to implement specific
functions.
Decoded audio data goes through a software vol-
ume control and a two-band equalizer blocks be-
fore feeding the output I2S interface. This results
in no need for an external audio processor.
MP3 bitstream is sent to the decoder using a sim-
ple serial input interface (see pins SDI, SCKR,
BIT_EN and DATA_REQ), supporting input rate
up to 20 Mbit/s. Received data are stored in a
256 bytes long input buffer which provides a
feedback line (see DATA_REQ pin) to the bit-
stream source (tipically an MCU).
1.2 - ADPCM encoder/decoder engine
This device also embeds a multistandard ADPCM
encoder/decoder supporting different sample
rates (from 8 KHz up to 32 KHz) and different
sample sizes (from 8 bit to 32 bits). During en-
coding process two different interfaces can be
used to feed data: the serial input interface (same
interface used also to feed MP3 bitstream) or the
ADC input interface, which provides a seamless
connection with an external A/D converter. The
currently used interface is selected via I2C bus.
Also to retrieve encoded data two different inter-
faces are available: the I2C bus or the faster
GPSO output interface. GPSO interface is able to
output data with a bitrate up to 5 Mbit/s and its
control pins (GPSO_SCKR, GPSO_DATA and
GPSO_REQ) can be configured in order to easily
fit the target application.
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
V
i
V
O
T
stg
T
oper
Parameter
Power Supply
Voltage on Input pins
Voltage on output pins
Storage Temperature
Operative ambient temp
Value
-0.3 to 4
-0.3 to V
DD
+0.3
-0.3 to V
DD
+0.3
-40 to +150
-20 to +85
Unit
V
V
V
°C
°C
THERMAL DATA
Symbol
R
th j-amb
Parameter
Thermal resistance Junction to Ambient
Value
85
Unit
°C/W
4/45
DSP 与 ARM 处理器
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