®
STA020
96kHz DIGITAL AUDIO INTERFACE TRANSMITTER
PRODUCT PREVIEW
MONOLITHIC DIGITAL AUDIO INTERFACE
TRANSMITTER
3.3V SUPPLY VOLTAGE
SUPPORTS:
- AES/EBU, IEC 958,
- S/PDIF, & EIAJ CP-340
- Professional and Consumer Formats
PARITY BITS AND CRC CODES GENERATED
TRANSPARENT MODE ALLOWS DIRECT
CONNECTION OF STA020 AND STA120
DESCRIPTION
The STA020 is a monolithic CMOS device which
encodes and transmits audio data according to
the AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340
interface standards. It supports 96kHz sample
rate operation
The STA020 accepts audio and digital data which
is then multiplexed, encoded and driven onto a
cable.
The audio serial port is double buffered and ca-
BLOCK DIAGRAM
SDIP24
SO24
ORDERING NUMBERS:
STA020
STA020D
pable of supporting a wide variety of formats.
The STA020 multiplexes the channel, user, and
validity data directly from serial input pins with
dedicated input pins for the most important chan-
nel status bits.
M0
23
SCK
FSYNC
SDATA
6
7
8
M1
22
M2
21
VD+
19
GND
18
MCK
5
RST
16
AUDIO
SERIAL PORT
MUX
DIFFERENTIAL
20
TXP
17
C
U
V
10
11
9
REGISTERS
7
TXN
15
DEDICATED CHANNEL CBL
STATUS BUS
24
TRNPT
D97AU599A
October 1999
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/12
STA020
PINS DESCRIPTION
(continued)
N.
8
Name
SDATA
Function
Serial Data.
Audio data serial input pin.
Serial Port Mode Select.
Selects the format of FSYNC and the sample edge of SCK with respect to SDATA.
Channel Status Bit 7/Channel Status Bit 3.
In professional mode, C7 is the inverse of channel status bit 7. In consumer mode, C3 is the
inverse of channel status bit 3, C7/C3 are ignored in Transparent Mode.
Professional/Consumer Select.
Selects between professional mode (PRO low) and consumer mode (PRO high). This pin
defines the functionality of the channel status parallel pins. PRO is ignored in Transparent
Mode.
Channel Status Bit 1/Frequency Control 0.
In professional mode, C1 is the inverse of channel status bit 1. In consumer mode, FC0 and
FC1 are encoded versions of channel status bits 24 and 25 (bits 0 and 1 of byte 3). When
FC0 and FC1 are both high, CD mode is selected. C1/FC0 are ignored in Transparent Mode.
Channel Status Bit 6/Channel Status Bit 2.
In professional mode, C6 is the inverse of channel status bit 6. In consumer mode, C2 is the
inverse of channel status bit 2. C6/C2 are ignored in Transparent Mode.
Validity.
Validity bit serial input port. This bit is defined as per the digital audio standards wherein V = 0
signifies the audio signal is suitable for conversion to analog. V = 1 signifies the audio signal is
not suitable for conversion to analog, i.e. invalid.
Channel Status Serial Input/Subcode Frame Clock.
In professional and consumer modes this pin is the channel status serial input port. In CD
mode this pin inputs the CD subcode frame clock.
User Bit.
User bit serial input port.
Channel Status Bit 9/Channel Status Bit 15.
In professional mode, C9 is the inverse of channel status bit 9 (bit 1 of byte 1). In consumer
mode, C15 is the inverse of channel status bit 15 (bit 7 of byte 1). C9/C15 are ignored in
Transparent Mode.
Emphasis 1/Channel Status Bit 8.
In professional mode, EM0 and EM1 encode channel status bits 2, 3 and 4. In consumer
mode, C8 is the inverse of channel status bit 8 (bit 0 of byte 1). EM1/C8 are ignored in
Transparent Mode.
Emphasis 0/Channel Status Bit 9.
In professional mode, EM0 and EM1 encode channel status bits 2, 3 and 4. In consumer
mode, C9 is the inverse of channel status bit 9 (bit 1 of byte 1). EM0/C9 are ignored in
Transparent Mode.
Channel Status Block Output/Subcode Bit Clock.
In professional and consumer modes, the channel status block output is high for the first 15
bytes of channel status. In CD mode, this pin outputs the subcode bit clock.
Master Reset.
When low, all internal counters are reset.
Transparent Mode/Frequency Control 1.
In professional mode, setting TRNPT low selects normal operation & CBL is an output. Setting
TRNPT high, allows the STA020 to be connected directly to an STA120. In transparent mode,
CBL is an input & MCK must be at 256 Fs. In consumer mode, FC0 and FC1 are encoded
versions of channel status bits 24 and 25. When FC0 and FC1 are both high, CD mode is
selected.
21,
M0, M1, M2
22,23
Control Pins
1
C7/C3
2
PRO
3
C1/FC0
4
C6/C2
9
V
10
C/SBF
11
12
U
C9/C15
13
EM1/C8
14
EM0/C9
15
CBL/SBC
16
24
RST
TRNPT/FC1
Transmitter Interface
5
MCK
Master Clock. Clock input at 128x the sample frequency which defines the transmit timing. In
trasparent mode MCK must be 256 Fs.
20, 17 TXP, TXN
Differential Line Drivers.
3/12
STA020
GENERAL DESCRIPTION
The STA020 is a monolithic CMOS circuit that en-
codes and transmits audio and digital data ac-
cording to the AES/EBU, IEC 958, S/PDIF, and
EIAJ CP-340 interface standards. The chip ac-
cepts audio and control data separately; multiplex
and biphase-mark encode the data internally and
drive it, directly or through a transformer, to a
transmission line.
The STA020 has dedicated pins for the most im-
portant control bits and a serial input port for the
C, U and V bits.
Line Drivers
The differential line drivers for STA020 are low
skew, low impedance, differential outputs capable
of driving 110Ohm transmission lines. (RS422
line driver compatible).
They can also be disabled by resetting the device
(RST = low).
STA020 DESCRIPTION
The STA020 accepts 16 to 24-bit audio samples
through a serial port configured in one of seven
formats; provides several pins dedicated to par-
ticular channel status bits and allows all channel
status, user and validity bits to be serially input
through port pins. This data is multiplexed, the
parity bit is generated and the bit stream is
biphase-mark encoded and driven through an
RS422 line driver.
The STA020 operates as a professional or con-
sumer interface transmitter selectable by pin 2,
PRO. As a professional interface device, the
dedicated channel status input pins are defined
according to the professional standard, and the
CRC code (C.S. byte 23) can be internally gener-
ated.
As a consumer device, the dedicated channel
status input pins are defined according to the
consumer standard. A submode provided under
the consumer mode is compact disk, CD, mode.
When transmitting data from a compact disk, the
CD subcode port can accept CD subcode data,
extract channel status information from it, and
transmit it as user data.
The master clock , MCK, controls timing for the
entire chip and must be 128xFs. As an example,
if stereo data is input to the STA020 at 44.1kHz,
MCK input must be 128 times that or 5.6448MHz.
Audio Serial Port
The audio serial port is used to enter audio data
and consists of three pins: SCK, SDATA and
FSYNC, SCK clocks in SDATA, which is double
buffered, while FSYNC delineates the audio sam-
ples and may indicate the particular channel, left
or right. To support many different interfaces, M2,
M1 and M0 select one of seven different formats
for the serial port. The coding is shown in Table 3
while the formats are shown in Figure 3.
Format 0 and 1 are designed to interface with
Crystal ADCs. Format 2 communicates with Mo-
torola and TI DSPs. Format 3 is reserved. Format
2
4 is compatible with the I S standard. Formats 5
and 6 make the STA020 look similar to existing
16- and 18-bit DACs and interpolation filters. For-
mat 7 is an MSB-last format and is conducive to
serial arithmetic. SCK and FSYNC are outputs in
Format 0 and inputs in all other formats. In For-
mat 2, the rising edge of FSYNC delineates sam-
ples and the falling edge must occur a minimum
of one bit period before or after the rising edge.
In all formats except 2, FSYNC contains left/right
information requiring both edges of FSYNC to de-
lineate samples. Formats 5 and 6 require a mini-
mum of 16- or 18-bit audio words respectively. In
all formats other than 5 and 6, the STA020 can
accept any word length from 16 to 24 bits by add-
ing leading zeros in format 7 and trailing zeros in
the other formats, or by restricting the number of
SCK periods between active edges of FSYNC to
the sample word length.
FSYNC must be derived from MCK, either
through a DSP using the same clock or using
counters. If SFYNC moves (jitters) with respect to
MCK by four MCK periods, the internal counters
and CBL may be reset.
Table 1. Audio Port Modes
M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
Format
0 - FSYNC & SCK Output
1 - Left/Right, 16-24 Bits
2 - Word Sync, 16-24 Bits
3 - Reserved
4 - Left/Right, I S Compatible
5 - LSB Justified, 16 Bits
6 - LSB Justified, 18 Bits
7 - MSB Last, 16-24 Bits
2
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