SigmaTel, Inc.
Integrating Mixed-Signal Solutions
Multimedia Audio Codec for AC’97
STAC9704/7
GENERAL DESCRIPTION:
SigmaTel’s
STAC9704/07
is a general purpose 18-bit, full duplex, audio codec that conforms to the analog
component specification of AC’97 (Audio Codec ’97 Component Specification rev. 1.03). The
STAC9704/07
incorporates
SigmaTel’s
proprietary Sigma-Delta technology to achieve signal quality in excess of
95dB
SNR.
The DACs, ADCs, and mixers are integrated with analog I/Os, which include four analog line-level stereo inputs,
two analog line-level mono inputs, and 3 output channels. Also included are
SigmaTel’s
3D stereo enhancement
(SS3D) and an extra true line-level out for headphones or speaker amplifiers. The
STAC9704/07
communicates
via the five wire AC Link to any digital component of AC’97 providing flexibility in the audio system design.
Packaged in a small AC’97 compliant 48-pin TQFP, the
STAC9704/07
can be placed on the motherboard,
daughter boards, add-on cards, PCMCIA cards, or outside the main chassis such as in a speaker. The 9707 is
identical to the 9704 except that the 9707 is tested at AVdd = DVdd = 3.3V.
FEATURES:
•
•
•
•
•
•
High performance
Σ ∆
technology
18-bit full duplex stereo A/D, D/A
AC-link protocol compliance
Single power source from 5V to 3.3V
AC'97 compliant mixer
SigmaTel Surround (SS3D)
Stereo
Enhancement
•
•
•
•
•
•
Energy saving power down modes
48k sample/second rate
Six analog line-level inputs
48-pin TQFP
SNR > 95 dB through Mixer and DAC
STAC9707 is the 3.3 volt version
1
10/02/98
ORDERING INFORMATION:
PART
NUMBER
STAC9704T
STAC9707T
PACKAGE
48-pin TQFP 7mm x 7mm x 1.4mm
48-pin TQFP 7mm x 7mm x 1.4mm
TEMPERATURE
RANGE
0o C to +70o C
0o C to +70o C
SUPPLY RANGE
DVdd = 3.3V – 5V, AVdd = 5V
DVdd = 3.3V
AVdd = 3.3V
SigmaTel reserves the right to change specifications without notice.
2
10/02/98
SigmaTel, Inc
Table of Contents
General Description
Ordering Information
1. PIN/SIGNAL Descriptions
1.1 Digital I/O
1.2 Analog I/O
1.3 Filter and Voltage References
1.4 Power and Ground Signals
2. AC-Link
2.1 Clocking
2.2 Reset
3. Digital Interface
3.1 AC-link Digital Serial Interface
Protocol
3.1.1 AC-link Audio Output Frame
(SDATA_OUT)
3.1.1.1 Slot 1: Command Address Port
3.1.1.2 Slot 2: Command Data Port
3.1.1.3 Slot 3: PCM Playback Left
Channel
3.1.1.4 Slot 4: PCM Playback Right
Channel
3.1.1.5 Slots 5-12: Reserved.
3.1.2 AC-link Audio Input Frame
(SDATA_IN)
3.1.2.1 Slot 1: Status Address Port
3.1.2.2 Slot 2: Status Data Port
3.1.2.3 Slot 3: PCM Record Left
Channel
3.1.2.4 Slot 4: PCM Record Right
Channel
3.1.2.5 Slots 5-12: Reserved
3.2 AC-link Low Power Mode
3.2.1 Waking up the AC-Link
1
2
8
8
9
10
11
11
12
12
12
12
STAC9704/7
4. STAC9704/7 Mixer
4.1 Mixer Input.
4.2 Mixer Output
4.3 PC Beep Implementations
4.4 Mixer Registers
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.4.8
4.4.9
Reset Register
Play Master Volume Registers
PC Beep Register
Analog Mixer Input Gain
Record Select Control
Record Gain Registers
General Purpose Register
3D Control Register
Powerdown Control/Status
21
23
23
23
24
25
25
25
26
26
28
28
29
29
30
32
32
32
33
34
35
36
36
37
38
38
38
39
39
40
42
44
45
5. Low Power Modes
6. Testability
7. AC Timing Characteristics
7.1 Cold Reset.
7.2 Warm Reset
7.3 Clocks
7.4 Data Setup and Hold
7.5 Signal Rise and Fall Times
7.6 AC-link Low Power Mode Timing
7.7 ATE Test Mode
8. Electrical Specifications
8.1 Absolute Maximum Ratings
8.2 Recommended Operating Conditions
8.3 Power Consumption
8.4 AC link Static Digital Specifications
8.5 9704 Analog Performance
Characteristics
8.6 9707 Analog Performance
Characteristics
APPENDIX A
APPENDIX B
14
16
16
16
17
17
17
19
19
19
19
20
20
21
3
10/02/98
SigmaTel, Inc
Table of Contents – Tables
Table 1 –
Package Dimensions
Table 2 –
Pin Designation
Table 3
– Digital Signal List
Table 4
– Analog Signal List
Table 5
– Filtering and Voltage References
Table 6
–Power Signal List STAC9704/07
Table 7
Table 8
– Mixer Functional Connections
Table 9
– Mixer Registers
Table 10
– Play Master Volume Register
Table 11
– PC Beep Register
Table 12
– Analog Mixer Input Gain Register
Table 13
– Record Select Control Registers
Table 14
– Record Gain Registers
Table 15
– General Purpose Register
Table 16
– 3D Control Register
Table 17
– Powerdown Status Register
Table 18
– Low Power Modes
Table 19
– Cold Reset
Table 20
– Warm Reset
Table 21
– Clocks
Table 22
– Data Setup and Hold
Table 23
– Signal Rise and Fall Times
Table 24
– AC-link Low Power Mode Timing
Table 25
– ATE Test Mode
Table 26
– Operating Conditions
Table 27
– Power Consumption
38
39
4
STAC9704/7
Table 28
– AC-link Static Specifications
5
5
8
9
10
11
Table 29
– 9704 Analog Performance
Characteristics
Table 30
– 9707 Analog Performance
Characteristics
39
40
42
Table of Contents – Figures
Figure 1
– Package Outline
Figure 2
– STAC9704 Block Diagram
Figure 3
– Connection Diagram
5
6
7
11
14
15
15
18
18
20
22
24
25
26
26
27
28
28
29
30
30
32
33
34
35
36
37
37
Figure 4
– STAC9704/07 AC’97 Link
Figure 5
– AC’97 Bi-directional Audio Frame
Figure 6
– AC-link Audio Output Frame
Figure 7
– Start of an Audio Output Frame
Figure 8
– STAC9704/07 Audio Input Frame
Figure 9
– Start of an Audio Input Frame
Figure 10
– STAC9704 Powerdown Timing
Figure 11
– STAC9704/07 Mixer Functional Diagram 22
Figure 12
– Example of STAC9704/07 Powerdown/
Powerup flow
Figure 13
– STAC9704/07 Powerdown/Powerup
with analog still alive
Figure 14
– Cold Reset
Figure 15
– Warm Reset
Figure 16
– Clocks
Figure 17
– Data Setup and Hold
Figure 18
– Signal Rise and Fall Times
Figure 19
– AC-link Low Power Mode Timing
Figure 20
– ATE Test Mode
31
31
32
33
34
35
36
36
37
10/02/98
SigmaTel, Inc
Figure 1 –
Package Outline
D
D1
STAC9704/7
Table 1
- Package Dimensions
KEY
26
a
38
SigmaTel
E
E1
e
STAC9704/7
48 pin TQFP
14
2
D
D1
E
E1
a (lead width)
e (pitch)
thickness
9704/7 DIMENSION
TQFP
9.00 mm
7.00 mm
9.00 mm
7.00 mm
0.20 mm
0.50 mm
1.4 mm
Table 2
- Pin Designation
PIN
#
1
2
3
4
5
6
7
8
9
10
11
12
SIGNAL
NAME
DVdd1
XTL_IN
XTL_OUT
DVss1
SDATA_OUT
BIT_CLK
DVss2
SDATA_IN
DVdd2
SYNC
RESET#
PC_BEEP
PI
N#
13
14
15
16
17
18
19
20
21
22
23
24
SIGNAL
NAME
PHONE
AUX_L
AUX_R
VIDEO_L
VIDEO_R
CD_L
CD_GND
CD_R
MIC1
MIC2
LINE_IN_L
LINE_IN_R
PIN
#
25
26
27
28
29
30
31
32
33
34
35
36
SIGNAL
NAME
AVdd1
AVss1
Vref
Vrefout
AFILT1
AFILT2
NC
CAP2
NC
NC
LINE_OUT_L
LINE_OUT_R
PIN
#
37
38
39
40
41
42
43
44
45
46
47
48
SIGNAL
NAME
MONO_OUT
AVdd2
LNLVL_OUT_L
NC
LNLVL_OUT_R
AVss2
NC
NC
NC
NC
NC
NC
# denotes active low
5
10/02/98
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
