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CAT28C16AGA-20

产品描述EEPROM, 2KX8, 200ns, Parallel, CMOS, PQCC32, LEAD AND HALOGEN FREE, PLASTIC, LCC-32
产品类别存储    存储   
文件大小416KB,共10页
制造商Catalyst
官网地址http://www.catalyst-semiconductor.com/
标准
下载文档 详细参数 全文预览

CAT28C16AGA-20概述

EEPROM, 2KX8, 200ns, Parallel, CMOS, PQCC32, LEAD AND HALOGEN FREE, PLASTIC, LCC-32

CAT28C16AGA-20规格参数

参数名称属性值
是否Rohs认证符合
厂商名称Catalyst
零件包装代码QFJ
包装说明QCCJ, LDCC32,.5X.6
针数32
Reach Compliance Codeunknown
ECCN代码EAR99
最长访问时间200 ns
命令用户界面NO
数据轮询YES
耐久性10000 Write/Erase Cycles
JESD-30 代码R-PQCC-J32
JESD-609代码e3
长度13.97 mm
内存密度16384 bit
内存集成电路类型EEPROM
内存宽度8
湿度敏感等级3
功能数量1
端子数量32
字数2048 words
字数代码2000
工作模式ASYNCHRONOUS
最高工作温度105 °C
最低工作温度-40 °C
组织2KX8
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装等效代码LDCC32,.5X.6
封装形状RECTANGULAR
封装形式CHIP CARRIER
并行/串行PARALLEL
峰值回流温度(摄氏度)260
电源5 V
编程电压5 V
认证状态Not Qualified
座面最大高度3.55 mm
最大待机电流0.0001 A
最大压摆率0.035 mA
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层MATTE TIN
端子形式J BEND
端子节距1.27 mm
端子位置QUAD
处于峰值回流温度下的最长时间40
切换位NO
宽度11.43 mm
最长写入周期时间 (tWC)10 ms

文档预览

下载PDF文档
CAT28C16A
16K-Bit CMOS PARALLEL EEPROM
FEATURES
I
Fast read access times: 90 ns, 120 ns, 200 ns
I
Low power CMOS cissipation:
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
I
End of write detection:
DATA
polling
I
Hardware write protection
I
CMOS and TTL compatible I/O
I
10,000 or 100,000 Program/erase cycles
I
10 or 100 year data retention
I
Commercial, industrial and automotive
–Active: 25 mA Max.
–Standby: 100
µ
A Max.
I
Simple write operation:
–On-chip address and data latches
–Self-timed write cycle with auto-clear
I
Fast write cycle time: 10ms max
temperature ranges
DESCRIPTION
The CAT28C16A is a fast, low power, 5V-only CMOS
Parallel EEPROM organized as 2K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and V
CC
power up/down write protection
eliminate additional timing and protection hardware.
DATA
Polling signals the start and end of the self-timed
write cycle. Additionally, the CAT28C16A features hard-
ware write protection.
The CAT28C16A is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 10,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 24-pin DIP and SOIC or 32-pin PLCC pack-
ages.
BLOCK DIAGRAM
A4–A10
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
2,048 x 8
EEPROM
ARRAY
VCC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
TIMER
DATA POLLING
I/O0–I/O7
A0–A3
ADDR. BUFFER
& LATCHES
COLUMN
DECODER
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1076, Rev. D

 
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