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54F 74F161A
54F 74F163A Synchronous Presettable Binary Counter
November 1994
54F 74F161A
54F 74F163A
Synchronous Presettable Binary Counter
General Description
The ’F161A and ’F163A are high-speed synchronous modu-
lo-16 binary counters They are synchronously presettable
for application in programmable dividers and have two types
of Count Enable inputs plus a Terminal Count output for
versatility in forming synchronous multi-stage counters The
’F161A has an asynchronous Master-Reset input that over-
rides all other inputs and forces the outputs LOW The
’F163A has a Synchronous Reset input that overrides
counting and parallel loading and allows the outputs to be
simultaneously reset on the rising edge of the clock The
’F161A and ’F163A are high-speed versions of the ’F161
and ’F163
Features
Y
Y
Y
Y
Synchronous counting and loading
High-speed synchronous expansion
Typical count frequency of 120 MHz
Guaranteed 4000V minimum ESD protection
Commercial
74F161APC
Military
Package
Number
N16E
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 150 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 150 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
54F161ADM (Note 2)
74F161ASC (Note 1)
74F161ASJ (Note 1)
54F161AFM (Note 2)
54F161ALM (Note 2)
74F163APC
54F163ADM (Note 2)
74F163ASC (Note 1)
74F163ASJ (Note 1)
54F163AFM (Note 2)
54F163ALM (Note 2)
J16A
M16A
M16D
W16A
E20A
N16E
J16A
M16A
M16D
W16A
E20A
Note 1
Devices also available in 13
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
reel Use suffix
e
SCX and SJX
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
’F161A
Pin Assignment
for LCC
’F161A
Pin Assignment
for DIP SOIC and Flatpak
’F163A
Pin Assignment
for LCC
’F163A
TL F 9486– 1
TL F 9486 – 2
TL F 9486 – 7
TL F 9486 – 8
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9486
RRD-B30M75 Printed in U S A
Logic Symbols
’F161A
’F163A
TL F 9486– 3
TL F 9486 – 9
IEEE IEC
’F161A
IEEE IEC
’F163A
TL F 9486– 6
TL F 9486 – 10
Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
10 10
10 20
10 10
10 10
10 20
10 10
10 20
50 33 3
50 33 3
Input I
IH
I
IL
Output I
OH
I
OL
20
mA
b
0 6 mA
20
mA
b
1 2 mA
20
mA
b
0 6 mA
20
mA
b
0 6 mA
20
mA
b
1 2 mA
20
mA
b
0 6 mA
20
mA
b
1 2 mA
b
1 mA 20 mA
b
1 mA 20 mA
CEP
CET
CP
MR (’F161A)
SR (’F163A)
P
0
–P
3
PE
Q
0
–Q
3
TC
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Synchronous Reset Input (Active LOW)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Flip-Flop Outputs
Terminal Count Output
2
Functional Description
The ’F161A and ’F163A count in modulo-16 binary se-
quence From state 15 (HHHH) they increment to state 0
(LLLL) The clock inputs of all flip-flops are driven in parallel
through a clock buffer Thus all changes of the Q outputs
(except due to Master Reset of the ’F161A) occur as a re-
sult of and synchronous with the LOW-to-HIGH transition
of the CP input signal The circuits have four fundamental
modes of operation in order of precedence asynchronous
reset (’F161A) synchronous reset (’F163A) parallel load
count-up and hold Five control inputs Master Reset (MR
’F161A) Synchronous Reset (SR ’F163A) Parallel Enable
(PE) Count Enable Parallel (CEP) and Count Enable Trickle
(CET) determine the mode of operation as shown in the
Mode Select Table A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW A LOW
signal on SR overrides counting and parallel loading and
allows all outputs to go LOW on the next rising edge of CP
A LOW signal on PE overrides counting and allows informa-
tion on the Parallel Data (P
n
) inputs to be loaded into the
flip-flops on the next rising edge of CP With PE and MR
(’F161A) or SR (’F163A) HIGH CEP and CET permit count-
ing when both are HIGH Conversely a LOW signal on ei-
ther CEP or CET inhibits counting
The ’F161A and ’F163A use D-type edge triggered flip-flops
and changing the SR PE CEP and CET inputs when the CP
is in either state does not cause errors provided that the
recommended setup and hold times with respect to the ris-
ing edge of CP are observed
The Terminal Count (TC) output is HIGH when CET is HIGH
and the counter is in state 15 To implement synchronous
multi-stage counters the TC outputs can be used with the
CEP and CET inputs in two different ways Please refer to
the ’F568 data sheet The TC output is subject to decoding
spikes due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous reset for
flip-flops counters or registers
Logic Equations Count Enable
e
CEP
CET
PE
TC
e
Q
0
Q
1
Q
2
Q
3
CET
State Diagram
Mode Select Table
SR
L
H
H
H
H
PE
X
L
H
H
H
CET
X
X
H
L
X
CEP
X
X
H
X
L
Action on the Rising
Clock Edge (L)
Reset (Clear)
Load (P
n
x
Q
n
)
Count (Increment)
No Change (Hold)
No Change (Hold)
For ’F163A only
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
TL F 9486 – 5
3
Block Diagram
4
TL F 9486 – 4
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