Preliminary Data Sheet
July 2000
T8533/34 Quad Programmable Line Card
Signal Processor
Features
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General Description
The quad programmable line card signal processor
consists of four independent channels of codec and
digital signal processing functions on one chip. In
addition to the classic A-to-D and D-to-A conversion,
the device includes termination impedance synthesis
and a 64-tap echo canceller, functionally, on a per-
channel basis. The device is capable of meeting all
international standards for terminating impedance
and digital encoding format. The processing circuitry
for the adjustment of the transmit level (equalization)
to accommodate current-sensing SLICs is also
included.
The device is controlled by a serial microprocessor
interface, and a set of bidirectional I/O pins are pro-
vided, on a per-channel basis, so that this control
mechanism can be utilized to operate the battery
feed device, ringing voltage switches, etc. Common
data and clock paths can be shared over any number
of devices. All the filter coefficients, signal process-
ing, SLIC, and test features are accessible through
this interface. This serial interface can be operated at
speeds up to 4.096 Mbits/s.
The PCM bus is also programmable, with any chan-
nel capable of being assigned to any time slot.
The PCM bus can be operated at speeds up to
16.384 Mbits/s, allowing for a maximum of 256 time
slots. Separate transmit and receive interfaces are
available for 4-wire bus designs, or they can be
strapped together for a 2-wire PCM bus.
The device is available in 68-pin, 64-pin, and 44-pin
surface-mount packages for economic use of board
space.
Includes codec, termination impedance, and echo
canceller in one device for line card applications
Programmable
µ-law,
linear, or A-law PCM input
and output (ITU-T G.712 compliant)
Per-channel programmable gains
Per-channel programmable internal termination
impedance
Per-channel 64-tap echo canceller (ITU-T G.168
compliant)
Fully programmable time-slot assignment
Analog and digital loopback test modes
Serial microprocessor interface
Sigma-delta converters with dither to reduce noise
Six per-channel, bidirectional control pins for SLIC
and line card function control (68-pin package)
Quad design to minimize package count on dense
line card applications
Built-in level correction (transmit equalization) to
accommodate current-sensing SLICs
Single 5 V operation
Available in 68-pin, 64-pin, and 44-pin packages
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T8533/34 Quad Programmable Line Card
Signal Processor
Preliminary Data Sheet
July 2000
Table of Contents
Contents
Page
Figure 8. Write Operation, Normal Mode
(Gapped DCLK) ........................................ 14
Figure 9. Write Operation, Byte-by-Byte Mode
(Continuous DCLK) .................................. 15
Figure 10. Write Operation, Byte-by-Byte Mode
(Gapped DCLK) ...................................... 15
Figure 11. Read Operation, Normal Mode
(Continuous DCLK) ................................. 16
Figure 12. Read Operation, Normal Mode
(Gapped Clock) ....................................... 17
Figure 13. Read Operation, Byte-by-Byte Mode
(Continuous DCLK) ................................. 18
Figure 14. Read Operation, Byte-by-Byte Mode
(Gapped DCLK) ...................................... 19
Figure 15. Fast Scan, Normal Mode
(Continuous DCLK) ................................. 20
Figure 16. Fast Scan, Normal Mode
(Gapped DCLK) ...................................... 21
Figure 17. Fast Scan, Byte-by-Byte Mode
(Continuous DCLK) ................................. 22
Figure 18. Fast Scan, Byte-by-Byte Mode
(Gapped DCLK) ...................................... 22
Figure 19. Hardware Reset Procedure .................... 23
Figure 20. Internal Signal Processing ...................... 26
Figure 21. Serial Interface Timing, Normal Mode
(One byte transfer shown.) ...................... 36
Figure 22. Byte-by-Byte Mode Timing ..................... 36
Figure 23. PCM Bus Timing .................................... 37
Figure 24. POTS Interface ....................................... 44
Features ......................................................................1
General Description.....................................................1
Functional Description .................................................3
Pin Information ............................................................5
Functional Description ...............................................11
Clocking Considerations .........................................11
The Control Interface ..............................................11
Modes ..................................................................11
Protocol ................................................................12
Write Command ...................................................14
Read Command ...................................................16
Fast Scan Mode ...................................................20
Write All Channels................................................23
Reset Functionality .................................................23
Memory Control Mapping .....................................24
Standby Mode.........................................................24
Test Capabilities .....................................................24
Echo Canceller Functionality ..................................25
SLIC Control Capabilities ........................................25
Suggested Initialization Procedures........................25
Signal Processing ...................................................26
Absolute Maximum Ratings.......................................26
Operating Ranges ....................................................27
Handling Precautions ................................................27
Electrical Characteristics ...........................................27
dc Characteristics ...................................................27
Analog Interface......................................................28
Transmission Characteristics ..................................29
Noise Characteristics ..............................................31
Distortion and Group Delay.....................................32
Crosstalk .................................................................33
Timing Characteristics ...............................................34
Bus Timing Diagrams ................................................36
Normal Mode ..........................................................36
Byte-by-Byte Mode .................................................36
PCM Interface .........................................................37
Applications ...............................................................44
Outline Diagrams.......................................................45
68-Pin PLCC ...........................................................45
64-Pin TQFP ...........................................................46
44-Pin PLCC ...........................................................47
Ordering Information..................................................48
Tables
Page
Figures
Page
Figure 1. Functional Block Diagram, Each
Section ........................................................3
Figure 2. 44-Pin PLCC Pin Diagram........................... 5
Figure 3. 68-Pin PLCC Pin Diagram ...........................7
Figure 4. 64-Pin TQFP Pin Diagram ...........................9
Figure 5. Command Frame Format, Master to Slave,
Read or Write Commands .........................13
Figure 6. Command Frame Format, Slave to Master,
Read Commands ......................................13
Figure 7. Write Operation, Normal Mode
(Continuous DCLK) ...................................14
2
Table 1. Pin Assignments, 44-Pin PLCC,
Per-Channel Functions ................................ 5
Table 2. Pin Assignments, 44-Pin PLCC,
Common Functions .................................... 6
Table 3. Pin Assignments, 68-Pin PLCC,
Per-Channel Functions ................................ 7
Table 4. Pin Assignments, 68-Pin PLCC,
Common Functions .................................... 8
Table 5. Pin Assignments, 64-Pin TQFP,
Per-Channel Functions ................................ 9
Table 6. Pin Assignments, 64-Pin TQFP,
Common Functions .................................. 10
Table 7. Bit Assignments for Fast Scan Mode ....... 20
Table 8. dc Characteristics ..................................... 27
Table 9. Analog Interface ....................................... 28
Table 10. Power Requirements .............................. 29
Table 11. Transmission Characteristics ................. 29
Table 12. Per-Channel Noise Characteristics ........ 31
Table 13. Distortion and Group Delay ..................... 32
Table 14. Crosstalk .................................................. 33
Table 15. Timing Characteristics ............................. 34
Table 16. Echo Canceller Characteristics ............... 35
Table 17. Memory Mapping ..................................... 38
Table 18. Control Bit Definition ................................ 39
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
T8533/34 Quad Programmable Line Card
Signal Processor
Functional Description
Refer to Figure 1 for the following discussion. (It should be noted that much of the processing is performed in a dig-
ital processor; thus, the actual data flow may be different than this functional, analog analogy based diagram
shows.)
ANALOG
GAIN
VF
X
INn
A/D
CONVERTER
DIGITAL
LOOPBACK 3
DIGITAL
LOOPBACK 2
ANALOG
LOOPBACK
DIGITAL GAIN
(GAIN TRANSFER)
PER
CHANNEL
18
COMMON
POWER AND
GROUND
–
DIGITAL
LOOPBACK 4
µ-LAW
OR
A-LAW
CONVERSION
DIGITAL
LOOPBACK 1
DX
TO/FROM
SLIC
TERMINATION
IMPEDANCE
ECHO
CancellER
PCM BUS
INTERFACE
TO/FROM
PCM BUS
VF
R
OPn
D/A
CONVERTER
VF
R
ONn
ANALOG
BUFFER
DIGITAL GAIN
(GAIN TRANSFER)
CONTROL AND DATA SIGNALS
FS
BCLK
DR
SLIC
CONTROL LATCHES
0 TO 6
PER
CHANNEL
MICROPROCESSOR CONTROL
FREQUENCY
SYNTHESIZER
3
FACTORY TEST
COMMON
4
RST
SERIAL
CONTROL
INTERFACE
5-7172.ar5(F)
MCLK
Figure 1. Functional Block Diagram, Each Section
This device performs virtually all the signal processing
functions associated with a central office line termina-
tion. Functionality includes line termination impedance
synthesis, adaptive or fixed hybrid balance (echo can-
celler), and level conversion both in the analog sense
(transmit equalization), to accommodate various sub-
scriber line interface circuits (SLICs), and in the digital
sense, for adjustment of the levels on the PCM bus
(gain transfer). In general, the termination impedance
synthesis generates the equivalent of a circuit with the
parallel combination of a capacitor and a resistor in
series with a resistor or the parallel combination of a
resistor and the series combination of a resistor and
capacitor. These general forms of impedance charac-
teristic will satisfy most of the requirements specified
throughout the world. Programmable selection of either
µ-law
or A-law encoding further aids worldwide deploy-
ment. In addition to the programmable features for
impedance and coding, the device also contains an
echo canceller that meets international requirements
for network echo cancellers. This includes the ability to
automatically disable the adaptation in the presence of
2100 Hz modem tones. All coefficients used in the fil-
tering algorithms can be computed off-line in advance
and downloaded to the device at the time of powerup.
All signal processing is contained within the device,
and there are only three interfaces of consequence to
the system designer: the SLIC interface, the PCM inter-
face, and the control interface.
Lucent Technologies Inc.
3
T8533/34 Quad Programmable Line Card
Signal Processor
Preliminary Data Sheet
July 2000
The microprocessor control interface is a serial inter-
face that uses the classic chip select type of operation.
The interface controls the device by writing or reading
various internal addresses. The command set com-
prises simple read and write operations, with the
address determining the effect. All the memory loca-
tions, including the per-chip functions, are organized by
channel, allowing a straightforward migration path to
architectures other than quad.
There are several test modes included to facilitate
confirmation of correct operation. In the signal path,
both an analog and four digital loopback tests are avail-
able, while in the microprocessor interface, there is a
write/read test mode that tests the operation of the
memory. Use of external test access switches allows a
complete test of the signal path through the line card so
that correct operation of various operational modes can
be verified.
Functional Description
(continued)
The SLIC interface is designed to be flexible and con-
venient to use with a variety of SLIC circuits. With an
appropriate choice of SLIC, no external components
are required in the interface, with the exception of a dc
blocking capacitor in the transmit direction. In some
cases, dc blocking capacitors in the receive direction
may be necessary as well, since the device operates
from a single 5 V supply.
The PCM bus interface is flexible in that it allows, inde-
pendently, the transmit and receive data for any chan-
nel to be placed in any time slot. The bus can be
operated at a maximum of a 16.384 Mbits/s rate to
accommodate a maximum of 256 time slots. Separate
pins are provided for each direction of transmission to
allow 4-wire bus operation. The frame strobe signal is
an 8 kHz signal that defines the beginning of the frame
structure. The interface will count 8 bits per time slot
and insert or read the data for each channel as pro-
grammed. Lower speeds of the PCM bus are allowed.
The PCM clock must be synchronous with the master
clock for the device (if present) and with the frame
strobe signal.
4
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
T8533/34 Quad Programmable Line Card
Signal Processor
Pin Information
DGND
MCLK
FILTV
DCLK
INTS
RST
V
DD
DO
6
PVCOIN
PVCO
PLLT
SGND
VF
R
ONa
VF
R
OPa
VF
X
Ia
V
DD
a
AGNDa
DGND
V
DD
7
8
9
10
11
12
13
14
15
16
17
5
4
3
2
1
44
43 42
41 40
39
38
37
36
35
DX
DGND
BCLK
FS
V
DD
VF
R
ONd
VF
R
OPd
VF
X
Id
V
DD
d
AGNDd
DGND
DR
34
33
32
31
30
29
28
V
DD
CS
DI
22
AGNDb
T8533
18 19
VF
R
ONb
VF
R
OPb
20
VF
X
Ib
21
V
DD
b
23
AGNDc
24
V
DD
c
25
VF
X
Ic
26
VF
R
OPc
27
VF
R
ONc
5-8195(F)
Figure 2. 44-Pin PLCC Pin Diagram
Table 1. Pin Assignments, 44-Pin PLCC, Per-Channel Functions
Ckt
a
b
c
d
15 22 23 30
14
13
12
11
21
20
19
18
24
25
26
27
31
32
33
34
Name
AGND
Type
Name/Description
GND
Analog Ground.
A common AGND, DGND, SGND plane is highly recom-
mended.
PWR
5 V Analog Power Supply.
V
DD
I
Transmit Analog Input.
VF
X
I
O
Receive Analog Output, Positive Polarity.
VF
R
OP
O
Receive Analog Output, Negative Polarity.
VF
R
ON
Lucent Technologies Inc.
5
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