HI-8483
February 2012
ARINC 429
Dual Line Receiver
PIN CONFIGURATIONS
(Top Views)
-V
S
- 1
TESTA - 2
CAP2B - 3
IN2B - 4
OUT2B - 5
IN2A - 6
CAP2A - 7
OUT2A - 8
+V
L
- 9
N/C - 10
20 - TESTB
19 - CAP1A
18 - IN1A
17 - CAP1B
16 - IN1B
15 - OUT1A
14 - GND
13 - N/C
12 - OUT1B
11 - +V
S
GENERAL DESCRIPTION
The HI-8483 bus interface unit is a dual differential line re-
ceiver in accordance with the requirements of the ARINC
429 bus specification. The device translates incoming
ARINC 429 signals to normal CMOS/TTL levels on each
of its two independent receive channels. The HI-8483 is
a functional alternative to the Fairchild/Raytheon
RM3283 and DEI3283.
Two TTL compatible self-test inputs for testing the ARINC
channels are available. They can be used to override the
ARINC input data and set the channel outputs to a known
state. The self-test mode checks the entire circuit includ-
ing the analog line receivers and digital logic.
All the ARINC inputs have built-in hysteresis to reject
noise that may be present on the ARINC bus. Additional
input noise filtering can also be accomplished with exter-
nal capacitors.
The HI-8483 is available in a variety of ceramic & plastic
packages including Small Outline (SOIC), DIP &
Leadless Chip Carrier (LCC).
HI-8483PSI
HI-8483PST
HI-8483PSM
20 - Pin Plastic Small Outline package (SOIC)
(See ordering information for additional pin configurations)
-V
S
- 1
TESTA - 2
CAP2B - 3
IN2B - 4
OUT2B - 5
IN2A - 6
CAP2A - 7
20 - TESTB
19 - CAP1A
18 - IN1A
17 - CAP1B
HI-8483CRI
HI-8483CRT
HI-8483CRM
16 - IN1B
15 - OUT1A
14 - GND
13 - N/C
12 - OUT1B
11 - +V
S
FEATURES
OUT2A - 8
+V
L
- 9
•
•
•
•
•
•
Replacement for RM3283 and DEI3283
Converts ARINC 429 levels to digital data
Input hysteresis for superior noise rejection
TTL and CMOS outputs and test inputs
Military screening available
20-Pin SOIC, DIP &
LCC packages are available
N/C - 10
20 - Pin Ceramic Dual In Line package (CERDIP)
(See ordering information for additional pin configurations)
TRUTH TABLE
ARINC INPUTS
V (A) - V (B)
Null
Zero
One
Don't Care
Don't Care
Don't Care
TEST INPUTS
TEST A
0
0
0
0
1
1
OUTPUTS
OUT A
0
0
1
0
1
0
TEST B
0
0
0
1
0
1
OUT B
0
1
0
1
0
0
(DS8483 Rev. A)
HOLT INTEGRATED CIRCUITS
www.holtic.com
02/12
HI-8483
PIN DESCRIPTIONS
SIGNAL
CAP1A
CAP1B
CAP2A
CAP2B
GND
IN1A
IN1B
IN2A
IN2B
OUT1A
OUT1B
OUT2A
OUT2B
TESTA
TESTB
+VL
+VS
-VS
FUNCTION
INPUT
INPUT
INPUT
INPUT
POWER
ARINC INPUT
ARINC INPUT
ARINC INPUT
ARINC INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
POWER
POWER
POWER
DESCRIPTION
Filter capacitor input for terminal A of channel 1
Filter capacitor input for terminal B of channel 1
Filter capacitor input for terminal A of channel 2
Filter capacitor input for terminal B of channel 2
Chip 0V supply
ARINC 429 input terminal A of channel 1
ARINC 429 input terminal B of channel 1
ARINC 429 input terminal A of channel 2
ARINC 429 input terminal B of channel 2
TTL output terminal A of channel 1
TTL output terminal B of channel 1
TTL output terminal A of channel 2
TTL output terminal B of channel 2
Test input terminal A
Test input terminal B
+5 Volts +/- 10%
+15 Volts +/- 10%
-15 Volts +/- 10%
BLOCK DIAGRAM
+VS
+VL
IN1A
IN1B
CAP1A
CAP1B
Bit Detection
and Level
Shifting
Hysteresis
Output
Driver
OUT1A
OUT1B
TESTA
TESTB
Channel
Test
Circuitry
Voltage Reference
Threshold
Generator
CAP2A
CAP2B
IN2A
IN2B
Bit Detection
and Level
Shifting
Hysteresis
Output
Driver
OUT2A
OUT2B
-VS
GND
FIGURE 1 - HI-8483 BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
2
HI-8483
FUNCTIONAL DESCRIPTION
The HI-8483 contains two independent ARINC 429 receive
channels, which take differently encoded ARINC level data
and convert it to serial TTL level data. The HI-8483 provides
two complete analog line receivers and no external
components are required.
Input level-shifting resistor networks allow ARINC input
voltage transients up to +/- 200V without damage to the HI-
8483.
Each channel is identical, featuring symmetrical delays for
better high-speed performance. Input common mode
rejection is excellent and threshold voltage is stable,
independent of supply voltage. Data outputs are TTL and
CMOS compatible.
Two TTL compatible test inputs (TESTA and TESTB) used
to simultaneously test both ARINC channels are available.
They can be used to override the ARINC input data and set
the channel outputs to a known state.
The HI-8483 contains two discrete ARINC 429 receiver
channels. Each channel contains three main sections: a
resistor input network, a window comparator, and a logic
output buffer stage. The first stage provides over-voltage
protection and biases the signal using voltage dividers,
providing excellent input common mode rejection. The
TESTA and TESTB inputs are provided to set the outputs to
a predetermined state for built-in channel test capability. If
the test inputs are not used they should be grounded.
The window comparator section detects data from the input
resistor network. An ARINC “high” state generates a logic
“1” at OUTA and an ARINC “low” state generates a logic “1”
at OUTB. An ARINC “null” state at the inputs forces both
outputs to logic “0”. Threshold and hysteresis voltages are
generated by an on-chip voltage reference to maintain
stable switching characteristics over temperature and
supply voltage variations.
The output stage generates a TTL compatible logic output
capable of driving 3 mA of load.
ARINC LEVELS
The ARINC 429 specification requires the following
detection levels:
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5V to +13V
+2.5V to -2.5V
-6.5V to -13V
The HI-8483 guarantees recognition of these levels with a
common mode voltage with respect to GND less than
±13V for the worst case condition.
NOISE
The input hysteresis is set to reject voltage level transi-
tions in the undefined region between the maximum
ZERO level and the minimum NULL level and the unde-
fined region between the maximum NULL level and the
minimum ONE level. Therefore, once a valid input
differential voltage threshold is detected, the outputs will
remain at a valid logic state until a new valid input voltage
is detected.
The noise filter capacitors are optional and are added to
provide extra noise immunity by limiting the bandwidth of
the input signal before it reaches the window comparator
stage. Two capacitors are required for each channel and
they must be of the same value. The suggested capacitor
value for 100KHz operation is 39 pF. For lower data rates,
larger values of capacitance may be used to yield better
noise performance. To get optimum performance, the
following equation can be used to calculate capacitor
value for a specific data rate:
C
FILTER
= 3.95 x 10
F
0
6
Where:
C
FILTER
is the capacitor value in pF
F
0
is the input frequency 10 KHz <= F
0
<= 150 KHz
HOLT INTEGRATED CIRCUITS
3
HI-8483
TYPICAL APPLICATIONS
APPLICATIONS
The standard connections for the HI-8483 are shown in
Figure 2. Decoupling of the supply should be done near the
IC to avoid propagation of noise spikes due to switching
transients. The ground (GND) connection should be sturdy
and isolated from large switching currents to provide a quiet
ground reference.
The HI-8483 can be used with HI-8570 or HI-8585 Line
Drivers to provide a complete analog ARINC 429 interface
solution. A simple application, which can be used in
systems requiring a repeater type circuit for long
transmissions or for test interfaces, is given in Figure 3.
More HI-8570 or HI-8585 drivers may be added to test
multiple ARINC channels, as shown.
+5V
+15V
HI-8483
ARINC
CHANNEL 1
39 pF
IN1A
IN1B
CAP1A
39 pF
OUT1A
OUT1B
A
B
CHANNEL 1
DATA OUT
TO LOGIC
CAP1B
IN2A
IN2B
OUT2A
OUT2B
A
B
CHANNEL 2
DATA OUT
TO LOGIC
ARINC
CHANNEL 2
39 pF
39 pF
CAP2A
CAP2B
TESTA
N/C
TESTB
N/C
LOGIC
TEST
INPUTS
-15V
FIGURE 2 - ARINC RECEIVER STANDARD CONNECTIONS
ARINC
INPUT
CHANNEL
IN1A
IN1B
OUT1A
OUT1B
DATA (A)
DATA (B)
AOUT
BOUT
A
B
ARINC
OUTPUT
CHANNEL 1
1/2
HI-8483
DATA (A)
DATA (B)
HI-8570
or HI-8585
AOUT
BOUT
A
B
ARINC
OUTPUT
CHANNEL 2
HI-8570
or HI-8585
TO ADDITIONAL
CHANNELS
FIGURE 3 - ARINC REPEATER CIRCUIT
HOLT INTEGRATED CIRCUITS
4
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