October 2012
ARINC 429
Transmitter / Dual Receiver for 8-Bit Bus
FEATURES
•
Single +5V supply
•
ARINC 429 protocol controller with 8-bit parallel
host interface
•
Automatic label recognition option
•
Programmable parity option
• Transmit FIFO for up to five ARINC 429 messages
•
CMOS / TTL logic pins
•
Industrial and Extended temperature ranges
•
Burn-in available
HI-6011
GENERAL DESCRIPTION
The HI-6011 is a CMOS integrated circuit designed to
interface the avionics ARINC 429 data bus to an 8-bit
port. It contains two receivers and one transmitter. They
operate independently except for the parity option and
the selected clock rate. The receiver demands that
the incoming data meet the standard protocol and the
transmitter outputs a standard protocol stream.
The HI-6011 provides flexible options for interfacing to
the user system. The controlling processor can operate
both the receiver and transmitter either by using hard
wired flags and gates at the pins or by using software
reads and writes of internal registers or a combination
thereof.
The chip is programmable to operate with single 8-bit
bytes where successive writes and reads are used to
receive or transmit complete 32 bit words.
The receiver allows two operational modes: Mode 0 to
allow receiving data words irrespective of the word’s
address label (first 8 Bits); Mode 1 to permit receiving
only words with matching address labels.
A Master clock signal of 1, 6 or 12 MHz is supplied to
the HI-6011. Two bits of the control word define the
frequency.
Interrupt error flags are generated for received parity
errors or premature (before 32 bits are received) idle
line conditions.
The HI-6011 is a 5 volt chip that will require data
translation from and to the ARINC bus using external
line drivers and line receivers. The HI-8591 line receiver
is available for the receiver side and the single supply
HI-8592 line driver is available for the transmitter side.
PIN CONFIGURATION (TOP VIEW)
XONE
XZERO
R1ONE
R1ZERO
R2ONE
R2ZERO
A2
A1
A0
D0
D1
D2
NC
NC
VDD
VSS
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
WR
RD
CLOCK
RST
XINT
VDD
VSS
RINT
CS
D7
D6
D5
D4
D3
VDD
VSS
NC
NC
NC
NC
40-pin ceramic side-braised DIP
APPLICATIONS
•
Avionics Data Communication
•
Serial to Parallel Conversion
•
Parallel to Serial Conversion
DS6011 Rev. New
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HI-6011
PIN DESCRIPTIONS
Table 1. Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Symbol
XONE
XZERO
R1ONE
R1ZERO
R2ONE
R2ZERO
A2
A1
A0
D0
D1
D2
NC
NC
V
DD
V
SS
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
V
DD
D3
D4
D5
Function
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
I/O
I/O
-
-
POWER
GROUND
-
-
-
-
-
-
-
-
GROUND
POWER
I/O
I/O
I/O
Description
Bipolar modulated serial output data
Bipolar modulated serial output data
Receiver 1 input data
Receiver 1 input data
Receiver 2 input data
Receiver 2 input data
Address Line Bit 2
Address Line Bit 1
Address Line Bit 0
Data Line Bit 0
Data Line Bit 1
Data Line Bit 2
No Connect
No Connect
5 Volts ±10%
Ground – Reference for all signals
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
Ground – Reference for all signals
5 Volts ±10%
Data Line Bit 3
Data Line Bit 4
Data Line Bit 5
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HI-6011
Pin
30
31
32
33
34
35
36
37
38
39
40
Symbol
D6
D7
CS
RINT
V
SS
V
DD
XINT
RST
CLOCK
RD
WR
Function
I/O
I/O
INPUT
OUTPUT
GROUND
POWER
OUTPUT
INPUT
INPUT
INPUT
INPUT
Description
Data Line Bit 6
Data Line Bit 7
Chip Select (Low True)
Receiver Interrupt
Ground – Reference for all signals
5 Volts ±10%
Transmitter Interrupt
Reset (Low True)
1, 6, or 12 MHz input clock
Read Strobe (Low True) (Data clocked on trailing edge)
Write Strobe (Low True) (Data clocked on trailing edge)
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HI-6011
ARINC 429 DATA FORMAT AND READ/WRITE CYCLES
The ARINC 429 specification defines the 32-bit word as shown in Figure
1, indicating the order in which bits appear
on the ARINC 429 data bus. ARINC bit 1 is defined as the label MSB, whereas the data field MSB is bit 31 as shown
below.
SD
SDI
I
MSB
ARINC bit #:
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 1. ARINC 429 Data Format.
Read/write operations to the HI-6011 are performed via 3 address pins, A2:0, and 8 data pins, D7:0. The address
pins A2:0 specify the possible read/write operations (see Section “Read/Write Operations”). The 32-bit ARINC word is
communicated using 4 successive reads or writes over the 8-bit data bus as follows:
Table 2. Order of ARINC 429 word bits during read/write cycles.
Read/Write
ARINC 429 bits
Cycle
1
2
3
4
Bits 1-8 (Label)
Bits 9-16
Bits 17-24
Bits 25-32
Data Pins D7:0
Bit 1 = D0, Bit 8 = D7
Bit 9 = D0, Bit 16 = D7
Bit 17 = D0, Bit 24 = D7
Bit 25 = D0, Bit 32 = D7
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PA
LABEL
LSB
LSB
DATA
MSB
R
IT
Y
HI-6011
READ/WRITE OPERATIONS
Read/write operations to the HI-6011 are performed via 3 address pins, A2:0, and 8 data pins, D7:0. The chip select
pin, CS, must be held low during all read/write operations. A single byte read is enabled by pulling the RD pin low.
Subsequent byte reads are performed by cycling RD high and then low for each additional byte read. Similarly, byte
writes are enabled in the same way by pulling the WR pin low and cycling high and then low for each additional byte
write. Table 3 and Table 4 summarize the address pins state for each permissible read and write operation respectively.
Table 3. Address pins A2:0 state for permissible read operations
Read to HI-6011: (CS = 0, RD = 0)
A2:0
000
Description
Read Interrupt Status Register. See Section “Interrupt Status Register”.
Read Receiver 1 data.
001
The 32-bit ARINC word is read using 4 successive reads over the 8-bit parallel bus, as outlined in Table
2. RD must be pulled low for the first byte read and then cycled high and low for subsequent byte reads.
CS should be held low during the entire 4-byte cycle.
If more than four reads are issued, the fifth re-reads the data originally read on the first read, etc.).
010
011
1xx
Read Receiver 2 data.
Same operation as Receiver 1 above.
Read Transmitter/General Status Register. See Section “Transmitter/General Status Register”.
No function. Returns all zeros.
Table 4. Address pins A2:0 state for permissible write operations
Write to HI-6011: (CS = 0, WR = 0)
A2:0
Description
Write Transmit FIFO.
The 32-bit ARINC word is written to the transmit FIFO using 4 successive writes over the 8-bit parallel
bus, as outlined in Table 2. WR must be pulled low for the first byte write and then cycled high and low
for subsequent byte writes. CS should be held low during the entire 4-byte cycle.
Bit 32 will be automatically overwritten with the correct parity.
Up to 5 32-bit words may be queued in the transmit FIFO. A minimum of 8μs must be allowed between
the last byte of each word (write cycle 4) and the first byte of the next word (write cycle 1). See Section
“Transmit FIFO Operation”.
000
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