HI-3584A
July 2013
ARINC 429 3.3V Serial Transmitter
and Dual Receiver with High-Speed Interface
APPLICATIONS
•
•
•
Avionics data communication
Serial to parallel conversion
Parallel to serial conversion
GENERAL DESCRIPTION
The HI-3584A from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a 16-bit parallel data bus to the
ARINC 429 serial bus. The HI-3584A design offers a high-
speed host CPU interface compared with the earlier HI-
3584 product. The device provides two receivers each with
label recognition, a 32 by 32 FIFO, and an analog line
receiver. Up to 16 labels may be programmed for each
receiver. The independent transmitter also has a 32 by 32
FIFO. The status of all three FIFOs can be monitored using
the external status pins or by polling the HI-3584A’s status
register.
Other features include a programmable option of data or
parity in the 32nd bit, and the ability to unscramble the 32 bit
word. Also, versions are available with different values of
input resistance to allow users to more easily add external
lightning protection circuitry.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus and all control
signals are CMOS and TTL compatible.
The HI-3584A applies the ARINC protocol to the receivers
and transmitter. Timing is based on a 1 Megahertz clock.
Additional interface circuitry such as the Holt HI-8570 or
HI-8571 is required to translate the transmitter’s 3.3 volt
logic outputs to ARINC 429 drive levels.
PIN CONFIGURATIONS
(Top View)
(See page 13 for additional pin configuration)
See Note below
64 - N/C
63 - RIN2B
62 - RIN2A
61 - RIN1B
60 - RIN1A
59 - N/C
58 - VDD
57 - VDD
56 - VDD
55 - N/C
54 - N/C
53 - MR
52 - TXCLK
51 - CLK
50 - RSR
49 - N/C
N/C - 1
D/R1 - 2
FF1 - 3
HF1 - 4
D/R2 - 5
FF2 - 6
HF2 - 7
SEL - 8
EN1 - 9
EN2 - 10
N/C - 11
BD15 - 12
BD14 - 13
BD13 - 14
BD12 - 15
BD11 - 16
HI-3584APCI
HI-3584APCT
&
HI-3584APCM
48 - CWSTR
47 - ENTX
46 - 429DO
45 - N/C
44 - N/C
43 - N/C
42 - N/C
41 - 429DO
40 - FFT
39 - HFT
38 - TX/R
37 - PL2
36 - PL1
35 - BD00
34 - BD01
33 - N/C
(Note: All 3 VDD pins must be connected to the same 3.3V supply)
64 - Pin Plastic 9mm x 9mm
Chip-Scale Package
52 - D/R1
51 - RIN2B
50 - RIN2A
49 - RIN1B
48 - RIN1A
47 - VDD
46 - N/C
45 - N/C
44 - MR
43 - TXCLK
42 - CLK
41 - RSR
40 - N/C
FEATURES
• ARINC specification 429 compatible
•
•
•
•
•
•
•
•
•
•
•
•
•
3.3V logic supply operation
Dual receiver and transmitter interface
Analog line receivers connect directly to ARINC bus
Programmable label recognition
On-chip 16 label memory for each receiver
32 x 32 FIFOs each receiver and transmitter
Independent data rate selection for transmitter
and each receiver
Status register
Data scramble control
32nd transmit bit can be data or parity
Self test mode
Low power
Industrial & Extended temperature ranges
FF1 - 1
HF1 - 2
D/R2 - 3
FF2 - 4
HF2 - 5
SEL - 6
EN1 - 7
EN2 - 8
BD15 - 9
BD14 - 10
BD13 - 11
BD12 - 12
BD11 - 13
N/C - 17
BD10 - 18
BD09 - 19
BD08 - 20
BD07 - 21
BD06 - 22
GND - 23
N/C - 24
N/C - 25
N/C - 26
N/C - 27
BD05 - 28
BD04 - 29
BD03 - 30
BD02 - 31
N/C - 32
HI-3584APQI
HI-3584APQT
&
HI-3584APQM
39 - N/C
38 - CWSTR
37 - ENTX
36 - N/C
35 - 429DO
34 - 429DO
33 - N/C
32 - FFT
31 - HFT
30 - TX/R
29 - PL2
28 - PL1
27 - BD00
52 - Pin Plastic Quad Flat Pack (PQFP)
(
(DS3584A Rev. C)
HOLT INTEGRATED CIRCUITS
www.holtic.com
BD10 - 14
BD09 - 15
BD08 - 16
BD07 - 17
BD06 - 18
N/C - 19
GND - 20
N/C - 21
BD05 - 22
BD04 - 23
BD03 - 24
BD02 - 25
BD01 - 26
0 7/13
HI-3584A
PIN DESCRIPTIONS
SIGNAL
VDD
RIN1A
RIN1B
RIN2A
RIN2B
D/R1
FF1
HF1
D/R2
FF2
HF2
SEL
EN1
EN2
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
GND
BD05
BD04
BD03
BD02
BD01
BD00
PL1
PL2
TX/R
HFT
FFT
429DO
429DO
ENTX
CWSTR
RSR
CLK
TX CLK
MR
FUNCTION
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
POWER
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
DESCRIPTION
+3.3V ±5% (All three VDD pins on the chip-scale package must be connect to the same supply)
ARINC receiver 1 positive input
ARINC receiver 1 negative input
ARINC receiver 2 positive input
ARINC receiver 2 negative input
Receiver 1 data ready flag
FIFO full Receiver 1
FIFO Half full, Receiver 1
Receiver 2 data ready flag
FIFO full Receiver 2
FIFO Half full, Receiver 2
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
Data Bus control, enables receiver 1 data to outputs
Data Bus control, enables receiver 2 data to outputs if EN1 is high
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
0V
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Latch enable for byte 1 entered from data bus to transmitter FIFO.
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after
transmission and FIFO empty.
Transmitter FIFO Half Full
Transmitter FIFO Full
“ONES” data output from transmitter
“ZEROS” data output from transmitter
Enable Transmission
Clock for control word register
Read Status Register if SEL=0, read Control Register if SEL=1
Master Clock input
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
HOLT INTEGRATED CIRCUITS
2
HI-3584A
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-3584A contains a 16-bit control register which is used to
configure the device. The control register bits CR0 - CR15 are
loaded from BD00 - BD15 when CWSTR is pulsed low. The con-
trol register contents are output on the databus when SEL = 1 and
RSR is pulsed low. Each bit of the control register has the follow-
ing function:
CR
Bit
CR0
STATUS REGISTER
The HI-3584A contains a 9-bit status register which can be interro-
gated to determine the status of the ARINC receivers, data FIFOs
and transmitter. The contents of the status register are output on
BD00 - BD08 when the RSR pin is taken low and SEL = 0. Unused
bits are output as zeros. The following table defines the status reg-
ister bits.
SR
FUNCTION
Receiver 1
Data clock
Select
Label Memory
Read / Write
STATE
0
1
0
1
DESCRIPTION
Data rate = CLK/10
Data rate = CLK/80
Normal operation
Load 16 labels using PL1 / PL2
Read 16 labels using EN1 / EN2
Disable label recognition
Bit
SR0
FUNCTION
Data ready
(Receiver 1)
STATE
0
1
DESCRIPTION
Receiver 1 FIFO empty
Receiver 1 FIFO contains valid data
Resets to zero when all data has
been read. D/R1 pin is the inverse of
this bit
Receiver 1 FIFO holds less than 16
words
Receiver 1 FIFO holds at least 16
words. HF1 pin is the inverse of
this bit.
Receiver 1 FIFO not full
Receiver 1 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period. FF1 pin is
the inverse of this bit
Receiver 2 FIFO empty
Receiver 2 FIFO contains valid data
Resets to zero when all data has
been read. D/R2 pin is the inverse of
this bit
Receiver 2 FIFO holds less than 16
words
Receiver 2 FIFO holds at least 16
words. HF2 pin is the inverse of
this bit.
Receiver 2 FIFO not full
Receiver 2 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period. FF2 pin is
the inverse of this bit
Transmitter FIFO not empty
Transmitter FIFO empty.
Transmitter FIFO not full
Transmitter FIFO full. FFT pin is the
inverse of this bit.
Transmitter FIFO contains less than
16 words
Transmitter FIFO contains at least
16 words.HFT pin is the
inverse of this bit.
CR1
SR1
FIFO half full
(Receiver 1)
0
1
CR2
Enable Label
Recognition
(Receiver 1)
Enable Label
Recognition
(Receiver 2)
Enable
32nd bit
as parity
Self Test
0
1
0
1
0
1
0
Enable label recognition
Disable Label Recognition
SR2
Enable Label recognition
Transmitter 32nd bit is data
Transmitter 32nd bit is parity
The 429DO and 429DO digital
outputs are internally connected
to the receiver logic inputs
Normal operation
Receiver 1 decoder disabled
SR4
ARINC bits 9 and 10 must match
CR7 and CR8
If receiver 1 decoder is enabled,
the ARINC bit 9 must match this bit
If receiver 1 decoder is enabled,
the ARINC bit 10 must match this bit
Receiver 2 decoder disabled
ARINC bits 9 and 10 must match
CR10 and CR11
SR6
If receiver 2 decoder is enabled,
the ARINC bit 9 must match this bit
If receiver 2 decoder is enabled,
the ARINC bit 10 must match this bit
Transmitter 32nd bit is Odd parity
Transmitter 32nd bit is Even parity
Data rate=CLK/10, O/P slope=1.5us
1
Data rate=CLK/80, O/P slope=10us
Data rate=CLK/10
Data rate=CLK/80
Scramble ARINC data
Unscramble ARINC data
SR8
Transmitter FIFO
half full
0
SR7
Transmitter FIFO
empty
Transmitter FIFO
full
0
1
0
1
SR5
FIFO full
(Receiver 2)
0
1
FIFO half full
(Receiver 2)
0
1
SR3
Data ready
(Receiver 2)
0
1
FIFO full
(Receiver 1)
0
1
CR3
CR4
CR5
1
CR6
Receiver 1
decoder
0
1
CR7
CR8
CR9
-
-
Receiver 2
Decoder
-
-
0
1
CR10
CR11
CR12
-
-
Invert
Transmitter
parity
Transmitter
data clock
select
Receiver 2
data clock
select
Data
format
-
-
0
1
0
1
0
1
0
1
CR13
CR14
CR15
HOLT INTEGRATED CIRCUITS
3
HI-3584A
FUNCTIONAL DESCRIPTION (cont.)
ARINC 429 DATA FORMAT
Control register bit CR15 is used to control how individual bits in the
received or transmitted ARINC word are mapped to the HI-3584A
data bus during data read or write operations. The following table
describes this mapping:
BYTE 1
DATA
BUS
ARINC
BIT
CR15=0
ARINC
BIT
CR15=1
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
13 12 11 10
9
31 30 32
1
2
3
4
5
6
7
8
The HI-3584A guarantees recognition of these levels with a common
mode Voltage with respect to GND less than ±4V for the worst case
condition (3.0V supply and 13V signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
RECEIVER LOGIC OPERATION
Figure 2 shows a block diagram of the logic section of each receiver.
BIT TIMING
The ARINC 429 specification contains the following timing specifi-
cation for the received data:
HIGH SPEED
LOW SPEED
100K BPS ± 1% 12K -14.5K BPS
BIT RATE
10 ± 5 µsec
PULSE RISE TIME
1.5 ± 0.5 µsec
10 ± 5 µsec
PULSE FALL TIME
1.5 ± 0.5 µsec
5 µsec ± 5% 34.5 to 41.7 µsec
PULSE WIDTH
The HI-3584A accepts signals that meet these specifications and re-
jects signals outside the tolerances. The way the logic operation
achieves this is described below:
1. Key to the performance of the timing checking logic is an ac-
curate 1MHz clock source. Less than 0.1% error is recom-
mended.
2. The sampling shift registers are 10 bits long and must show
three consecutive Ones, Zeros or Nulls to be considered valid
data. Additionally, for data bits, the One or Zero in the upper
bits of the sampling shift registers must be followed by a Null in
the lower bits within the data bit time. For a Null in the word gap,
three consecutive Nulls must be found in both the upper and
lower bits of the sampling shift register. In this manner the mini-
mum pulse width is guaranteed.
Parity
16 15 14 13 12 11 10
9
Label
8
Label
7
Label
6
Label
5
Label
4
Label
3
Label
2
BYTE 2
DATA
BUS
ARINC
BIT
CR15=0
ARINC
BIT
CR15=1
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
Parity
Label
Label
Label
Label
Label
Label
Label
Label
SDI
SDI
Label
1
SDI
SDI
3. Each data bit must follow its predecessor by not less than 8
samples and no more than 12 samples. In this manner the bit
rate is checked. With exactly 1MHz input clock frequency, the
acceptable data bit rates are as follows:
HIGH SPEED
ONES
V
DD
RIN1A
OR
RIN2A
GND
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
LOW SPEED
10.4K BPS
15.6K BPS
DATA BIT RATE MIN
DATA BIT RATE MAX
83K BPS
125K BPS
NULL
V
DD
RIN1B
OR
RIN2B
GND
ZEROES
4. The Word Gap timer samples the Null shift register every 10
input clocks (80 for low speed) after the last data bit of a valid
reception. If the Null is present, the Word Gap counter is
incremented. A count of 3 will enable the next reception.
FIGURE 1. ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS
4
HI-3584A
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER PARITY
The 32nd bit of received ARINC words stored in the receive FIFO
is used as a Parity Flag indicating whether good Odd parity is
received from the incoming ARINC word.
Odd Parity Received
The parity bit is reset to indicate correct parity was received
and the resulting word is then written to the receive FIFO.
Even Parity Received
The receiver sets the 32nd bit to a “1”, indicating a parity error
and the resulting word is then written to the receive FIFO.
Therefore, the 32nd bit retrieved from the receiver FIFO will
always be “0” when valid (odd parity) ARINC 429 words are
received.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending upon the state of control
register bits CR2-CR11, the received ARINC 32-bit word is then
checked for correct decoding and label matching before being
loaded into the 32 x 32 receive FIFO.
ARINC words which do not meet the necessary 9th and 10th
ARINC bit or label matching are ignored and are not loaded into
the receive FIFO. The following table describes this operation.
CR2(3) ARINC word CR6(9) ARINC word
matches
bits 9,10
label
match
CR7,8 (10,11)
0
1
1
0
0
1
1
1
1
X
No
Yes
X
X
Yes
No
No
Yes
0
0
0
1
1
1
1
1
1
X
X
X
No
Yes
No
Yes
No
Yes
FIFO
Load FIFO
Ignore data
Load FIFO
Ignore data
Load FIFO
Ignore data
Ignore data
Ignore data
Load FIFO
TO PINS
SEL
EN
MUX
CONTRO
L
32 TO 16 DRIVER
R/W
CONTROL
CONTROL
BITS
HF
FF
D/R
FIFO
LOAD
CONTROL
32 X 32
FIFO
CONTROL
BIT
/
16 x 8
LABEL
MEMORY
LABEL /
DECODE
COMPARE
CONTROLBITS
CR0, CR14
CLOCK
OPTION
CLOCK
CLK
32 BIT SHIFT REGISTER
DATA
BIT CLOCK
PARITY
CHECK
32ND
BIT
BIT
COUNTER
AND
END OF
SEQUENCE
EOS
ONES
SHIFT REGISTER
WORD GAP
WORD GAP
TIMER
BIT CLOCK
START
NULL
SHIFT REGISTER
SEQUENCE
CONTROL
END
ZEROS
SHIFT REGISTER
ERROR
ERROR
DETECTION
CLOCK
FIGURE 2.
RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
5
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