HI-3282, HI-3282B
July 2013
ARINC 429
Serial Transmitter and Dual Receiver
FEATURES
• ARINC specification 429 compatible
• Compatible with Industry-standard alternate
parts
• Small footprint 44-pin PQFP package option
• 16-Bit parallel data bus
• Direct receiver interface to ARINC bus
• Internal Lightning Protection of ARINC inputs
per DO-160D, Level 3 in -10 configurations
• Timing control 10 times the data rate
• Selectable data clocks
• Automatic transmitter data timing
• Self test mode
• Parity functions
• Low power, single 5 volt supply
• Industrial & extended temperature ranges
GENERAL DESCRIPTION
The HI-3282 is a silicon gate CMOS device for interfacing
the ARINC 429 serial data bus to a 16-bit parallel data bus.
Two receivers and an independent transmitter are
provided. The receiver input circuitry and logic are
designed to meet the ARINC 429 specifications for loading,
level detection, timing, and protocol. The ARINC inputs of
the HI-3282-10 configurations also have internal lightning
protection to DO-160D, Level 3. The transmitter section
provides the ARINC 429 communication protocol. An
external ARINC 429 Line Driver such as the Holt HI-3182 or
HI-8585 is required to translate the 5 volt logic outputs to
ARINC 429 drive levels.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The data bus interfaces with
CMOS and TTL.
Timing of all the circuitry begins with the master clock input,
CLK. For ARINC 429 applications, the master clock
frequency is 1 MHz.
Each independent receiver monitors the data stream with a
sampling rate 10 times the data rate. The sampling rate is
software selectable at either 1MHz or 125KHz. The results
of a parity check are available as the 32nd ARINC bit.
The transmitter has a First In, First Out (FIFO) memory to
store 8 ARINC words for transmission. The data rate of the
transmitter is software selectable by dividing the master
clock, CLK, by either 10 or 80. The master clock is used to
set the timing of the ARINC transmission within the required
resolution.
The HI-3282BPJx product has a minimum low speed data
rate of 6.5K BPS.
PIN CONFIGURATION
(Top View)
- N/C
- 429DI2(B)
- 429DI2(A)
- 429DI1(B)
- 429DI1(A)
- VCC
- DBCEN
- MR
- TXCLK
- CLK
- N/C
N/C - 1
D/R1 - 2
D/R2 - 3
SEL - 4
EN1 - 5
EN2 - 6
BD15 - 7
BD14 - 8
BD13 - 9
BD12 - 10
BD11 - 11
44
43
42
41
40
39
38
37
36
35
34
HI-3282PQI
HI-3282PQI-10
HI-3282PQT
&
HI-3282PQT-10
APPLICATIONS
•
Avionics data communication
33 - N/C
32 - N/C
31 - CWSTRX
30 - ENTX
29 - 429DO
28 -429DO
27 - TX/R
26 - PL2
25 - PL1
24 - BD00
23 - BD01
• Serial to parallel conversion
• Parallel to serial conversion
44-Pin Plastic Quad Flat Pack (PQFP)
(See page 10 for additional pin configurations)
(DS3282 Rev. O)
(
HOLT INTEGRATED CIRCUITS
www.holtic.com
N/C - 12
BD10 - 13
BD09 - 14
BD08 - 15
BD07 - 16
BD06 - 17
GND - 18
BD05 - 19
BD04 - 20
BD03 - 21
BD02 - 22
07/13
HI-3282, HI-3282B
PIN DESCRIPTION
SYMBOL
VCC
429DI1 (A)
429DI1 (B)
429DI2 (A)
429DI2 (B)
D/R1
D/R2
SEL
EN1
EN2
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
GND
BD05
BD04
BD03
BD02
BD01
BD00
PL1
PL2
TX/R
429DO
429DO
ENTX
CWSTR
CLK
TX CLK
MR
DBCEN
FUNCTION
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
POWER
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
+5V ±5%
DESCRIPTION
ARINC receiver 1 positive input
ARINC receiver 1 negative input
ARINC receiver 2 positive input
ARINC receiver 2 negative input
Receiver 1 data ready flag
Receiver 2 data ready flag
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
Data Bus control, enables receiver 1 data to outputs
Data Bus control, enables receiver 2 data to outputs if EN1 is high
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
0V
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Latch enable for byte 1 entered from data bus to transmitter FIFO.
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
after transmission and FIFO empty.
"ONES" data output from transmitter.
"ZEROES" data output from transmitter.
Enable Transmission
Clock for control word register
Master Clock input
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
Data bit control Enable. (Active low, with internal pull up to VDD).
HOLT INTEGRATED CIRCUITS
2
HI-3282, HI-3282B
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-3282 contains 11 data flip flops whose D inputs are con-
nected to the data bus and clocks connected to CWSTR. Each
flip flop provides options to the user as follows:
DATA
BUS
PIN
BD04
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with
the receiver or the transmitter. ARINC bit 1 is the first bit
transmitted or received.
BYTE 1
DATA
BUS
ARINC
BIT
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
13 12 11 10
9
31 30 32
1
2
3
4
5
6
7
8
FUNCTION CONTROL
PAREN
DESCRIPTION
Enables parity bit insertion into
Transmitter data bit 32
If enabled, an internal connection
is made passing 429DO and
429DO to the receiver logic inputs
If enabled, ARINC bits 9 and,
10 must match the next two
control word bits
If Receiver 1 Decoder is
enabled, the ARINC bit 9
must match this bit
If Receiver 1 Decoder is
enabled, the ARINC bit 10
must match this bit
If enabled, ARINC bits 9 and
10 must match the next two
control word bits
If Receiver 2 Decoder is
enabled, then ARINC bit 9
must match this bit
If Receiver 2 Decoder is
enabled, then ARINC bit 10
must match this bit
Logic 0 enables normal odd parity
and Logic 1 enables even parity
output in transmitter 32nd bit
CLK is divided either by 10 or
80 to obtain XMTR data clock
CLK is divided either by 10 or
80 to obtain RCVR data clock
BYTE 2
DATA
BUS
ARINC
BIT
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
BDO5
SELF TEST
0 = ENABLE
BDO6
RECEIVER 1
DECODER
1 = ENABLE
RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
BDO7
-
-
BDO8
-
-
BDO9
RECEIVER 2
DECODER
1 = ENABLE
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
BD10
-
-
BD11
-
-
The HI-3282 guarantees recognition of these levels with a common
mode Voltage with respect to GND less than ±5V for the worst case
condition (4.75V supply and 13V signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
BD12
INVERT
XMTR
PARITY
XMTR DATA
CLK SELECT
RCVR DTA
CLK SELECT
1 = ENABLE
BD13
0 = ÷10
1 = ÷80
0 = ÷10
1 = ÷80
RECEIVER LOGIC OPERATION
Figure 2 shows a block diagram of the logic section of each receiver.
BD14
v
cc
429DI1 (A)
OR
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
ONES
429DI2 (A)
GND
NULL
v
cc
429DI1 (B)
OR
ZEROES
429DI2 (B)
GND
FIGURE 1.
ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS
3
HI-3282, HI-3282B
FUNCTIONAL DESCRIPTION (cont.)
BIT TIMING
The ARINC 429 specification contains the following timing
specification for the received data:
HIGH SPEED
LOW SPEED
BIT RATE
100K BPS ± 1% 12K -14.5K BPS
(HI-3282BPJx-xx only - 6.5K BPS min.)
PULSE RISE TIME
1.5 ± 0.5 µsec
10 ± 5 µsec
PULSE FALL TIME
1.5 ± 0.5 µsec
10 ± 5 µsec
PULSE WIDTH
5 µsec ± 5% 34.5 to 41.7 µsec
(HI-3282BPJx-xx only - 76.9 µsec max.)
data ready flag flip flop to a "1", D/R1 or D/R2 (or both) will go low.
The data flag for a receiver will remain low until after both ARINC
bytes from that receiver are retrieved. This is accomplished by
activating EN with SEL, the byte selector, low to retrieve the first
byte and activating EN with SEL high to retrieve the second byte.
EN1 retrieves data from receiver 1 and EN2 retrieves data from
receiver 2. If another ARINC word is received and a new EOS
occurs before the two bytes are retrieved, the data is overwritten
by the new word.
INTERNAL LIGHTNING PROTECTION (-10 Only)
The HI-3282-10 configurations are similar to the HI-3282 with the
exception that it allows an external 10K to 15K ohm resistor to be
added in series with each ARINC input without affecting the
ARINC input thresholds. This option is especially useful in
applications where lightning protection circuitry is also required.
The design of the HI-3282-10 device requires the external
10K to 15K ohm series resistors for proper ARINC level detection.
The typical 10 volt differential signal is translated and input to a
window comparator and latch. The comparator levels are set so
that, with the external 10K to 15K ohm resistors, they are just
below the standard 6.5 V minimum ARINC data threshold and just
above the 2.5 V maximum ARINC null threshold.
The receivers of the HI-3282-10 when used with external
15K ohm resistors will withstand DO-160F, Level 3, waveforms 3,
4, 5A and 5B. No additional lightning protection circuit is
necessary.
RECEIVER PARITY
The 32nd bit of received ARINC words stored in the receive FIFO
is used as a Parity Flag indicating whether good Odd parity is re-
ceived from the incoming ARINC word.
Odd Parity Received
The parity bit is reset to indicate correct parity was received
and the resulting word is then written to the receive FIFO.
Even Parity Received
The receiver sets the 32nd bit to a “1”, indicating a parity error
and the resulting word is then written to the receive FIFO.
Therefore, the 32nd bit retrieved from the receiver FIFO will always
be a “0” when valid (odd parity) ARINC 429 words are received.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). If the receiver decoder is enabled and
the 9th and 10th ARINC bits match the control word program bits
or if the receiver decoder is disabled, then the EOS clocks the
APPLICATION NOTE 300
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
Line Drivers and Receivers.
TO PINS
SEL
EN
D/R
DECODER
CONTROL
BITS
MUX
CONTROL
32 TO 16 DRIVER
CONTROL
BIT BD14
CLOCK
OPTION
CLOCK
CLK
/
LATCH
ENABLE
CONTROL
BITS 9 & 10
32 BIT LATCH
BIT
COUNTER
AND
END OF
SEQUENCE
32 BIT SHIFT REGISTER
DATA
PARITY
CHECK
32ND
BIT
BIT CLOCK
EOS
EOS
ONES
WORD GAP
WORD GAP
TIMER
BIT CLOCK
SHIFT REGISTER
START
END
NULL
SHIFT REGISTER
SEQUENCE
CONTROL
ZEROS
SHIFT REGISTER
ERROR
ERROR
DETECTION
CLOCK
FIGURE 2.
RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
4
HI-3282, HI-3282B
FUNCTIONAL DESCRIPTION (cont.)
TRANSMITTER
A block diagram of the transmitter section is shown in Figure 3.
The parity generator counts the ONES in the 31-bit word. If the BD12
control word bit is set low, the 32nd bit transmitted will make parity
odd. If the control bit is high, the parity is even.
SELF TEST
If the BD05 control word bit is set low, 429DO or 429DO are internally
connected to the receivers inputs, bypassing the interface circuitry.
Data to Receiver 1 is as transmitted and data to Recevier 2 is the
complement. 429DO and 429DO outputs remain active during self
test.
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1
and then PL2 to load byte 2. The control logic automatically loads
the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag, is high (FIFO empty), then 8 words,
each 31 bits long, may be loaded. If TX/R is low, then only the
available positions may be loaded. If all 8 positions are full, the
FIFO ignores further attempts to load data.
SYSTEM OPERATION
The two receivers are independent of the transmitter. Therefore,
control of data exchanges is strictly at the option of the user. The only
restrictions are:
1. The received data may be overwritten if not retrieved within
one ARINC word cycle.
2. The FIFO can store 8 words maximum and ignores attempts
to load addition data if full.
3. Byte 1 of the transmitter data must be loaded first.
4. Either byte of the received data may be retrieved first. Both
bytes must be retrieved to clear the data ready flag.
5. After ENTX, transmission enable, goes high it cannot go low
until TX/R, transmitter ready flag, goes high. Otherwise, one
ARINC word is lost during transmission.
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at either 429DO or 429DO. The 31 bits in the
data transmission shift register are presented sequentially to the
outputs in the ARINC 429 format with the following timing:
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
The word counter detects when all loaded positions are
transmitted and sets the transmitter ready flag, TX/R, high.
TRANSMITTER PARITY
Control register bit BD04 (PAREN) enables parity bit insertion into
transmitter data bit 32. Parity is always inserted if DBCEN is open
or high. If DBCEN is low, logic 0 on PAREN inserts data on bit 32,
and logic 1 on PAREN inserts parity on bit 32.
DBCEN
CONTROL REGISTER BD04, BD12
BIT CLOCK
MASTER RESET (MR)
On a Master Reset data transmission and reception are immedi-
ately terminated, the transmit FIFO and receivers cleared as are
the transmit and receive flags. The Control Register is not affected
by a Master Reset.
PARITY
GENERATOR
DATA AND
NULL TIMER
SEQUENCER
429DO
429DO
31 BIT PARALLEL
LOAD SHIFT REGISTER
WORD CLOCK
BIT
AND
WORD GAP
COUNTER
START
SEQUENCE
ADDRESS
8 X 31 FIFO
WORD COUNTER
AND
FIFO CONTROL
INCREMENT
WORD COUNT
TX/R
ENTX
LOAD
FIFO
LOADING
SEQUENCER
DATA
CLOCK
PL1
PL2
CLK
TX CLK
DATA CLOCK
DIVIDER
DATA BUS
FIGURE 3.
TRANSMITTER BLOCK DIAGRAM
CONTROL REGISTER
BIT BD13
HOLT INTEGRATED CIRCUITS
5
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