HI-3210
May 2011
ARINC 429 DATA MANAGEMENT ENGINE /
Octal Receiver / Quad Transmitter
FEATURES
•
Eight ARINC 429 Receive channels
•
Four ARINC 429 Transmit channels
•
32KB on chip user-configurable data storage
memory
GENERAL DESCRIPTION
The HI-3210 from Holt Integrated Circuits is a single chip
CMOS data management IC capable of managing, storing
and forwarding avionics data messages between eight
ARINC 429 receive channels and four ARINC 429 transmit
channels.
The ARINC 429 buses may be operated independently,
allowing a host CPU to send and receive data on multiple
buses, or the HI-3210 can be programmed to automati-
cally re-format, re-label, re-packetize and re-transmit data
from ARINC 429 receive buses to ARINC 429 transmit
buses.
A 32K x 8 on-board memory allows received data to be
logically organized and automatically updated as new
ARINC 429 labels are received.
An auto-initialization feature allows configuration informa-
tion to be up-loaded from an external EEPROM on reset to
facilitate rapid start-up or operation without a host CPU.
The HI-3210 interfaces directly with Holt’s HI-8448 octal
ARINC 429 receiver IC and HI-8592 or HI-8596 ARINC
429 line drivers.
•
Programmable received data filtering
•
Programmable transmission schedulers for periodic
ARINC 429 broadcasting
•
SPI Host CPU interface
•
Auto-initialization feature allows power-on
configuration or independent operation without CPU
PIN CONFIGURATION
ARX2P
ARX1N
ARX1P
ARX0N
ARX0P
SCANEN
ARXBIT5
READY
ESCLK
EMOSI
ECSB
EMISO
RUN
ARXBIT4
ATXMSK
MRST
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
APPLICATION
CPU
HI-8448
Memory
ARINC 429
4 x Transmit
ARINC 429
8 x Receive
AACK 1
ARXBIT6 2
AINT 3
ARXBIT7 4
SCANSHIFT 5
ARX2N 6
ARX3P 7
VDD 8
GND 9
ARX3N 10
ARX4P 11
ARX4N 12
ARX5P 13
ARX5N 14
ARX6P 15
ARX6N 16
HI-3210PQI
&
HI-3210PQT
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
ARXBIT3
ATXSLP0
ATX0N
ATX0P
ATX1N
ATX1P
ATXSLP1
VDD
GND
ARXBIT2
ATXSLP2
ATX2N
ATX2P
ATX3N
ATX3P
ATXSLP3
Controller
HI-3210
64 - Pin Plastic Quad Flat Pack (PQFP)
(See ordering information for additional pin configurations)
(DS3210 Rev. New)
ARX7P
ARX7N
MODE0
MODE1
MCLK
MODE2
ARXBIT0
VDD
GND
ARXBIT1
HMISO
HSCLK
HMOSI
HCSB
MINT
MINTACK
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
05/11
HI-3210
BLOCK DIAGRAM
Host CPU
MINTACK
MINT
ARINC 429
BIT MATCH
ARXBIT7
ARXBIT6
ARXBIT5
ARXBIT4
ARXBIT3
ARXBIT2
ARXBIT1
ARXBIT0
ARINC 429
RECEIVE DATA
MEMORY 0
1K x 8
HCSB
HSCLK
HMOSI
HMISO
ARINC 429
Interrupt Handler
AACK
AINT
SPI
Programmable
Interrupts
4 x ARINC 429 Transmit Buses
ARINC 429
Descriptor Table 0
ARINC 429
TRANSMIT
SCHEDULER 0
TRANSMITTER 0
8 x ARINC 429 Receive Buses
RECEIVER 0
FILTER
TABLE 0
TRANSMIT TIMER
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
32 x 32 FIFO
LABEL
FILTER
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
Message 32
“
“
“
Message 2
Message 1
EEPROM
SPI
HI-3210
ECSB
ESCLK
EMOSI
EMISO
Auto-Initialization
EEPROM
HOLT INTEGRATED CIRCUITS
2
HI-3210
APPLICATION OVERVIEW
The HI-3210 is a flexible device for managing ARINC 429
communications and data storage in many avionics
applications. The device architecture centers around a
32K x 8 static RAM used for data storage, data filtering
tables and table-driven transmission schedulers. Once
configured, the device can operate autonomously without
a host CPU, negating the need for software development
or DO-178 certification. Configuration data may be
uploaded into the device from an external EEPROM,
following system reset.
The device supports up to eight ARINC 429 receive
channels. Received data is stored in on-chip RAM
organized by channel number and label. The data table
continually updates as new labels arrive. Programmable
interrupts and filters alert the host subsystem to labels of
interest.
Each ARINC 429 receive channel also includes a 32
message deep FIFO allowing selected label data to be
queued for subsequent host access.
The HI-3210 includes four independent ARINC 429
transmit channels. Transmission may be controlled
entirely by an external CPU, or autonomously by
programming one or more of the four on-chip ARINC 429
transmit schedulers. These allow periodic transmission
to occur without CPU. Source data for transmission may
be selected from RAM based tables of constants and / or
from the received channel data. Powerful options exist for
constructing ARINC 429 labels as well as controlling their
timing and conditional transmission.
Even when running under the control of schedulers, the
host CPU may insert new labels for transmission at will.
The following examples show five possible configurations
of how the HI-3210 may be used:
Example 1. ARINC 429 Data reception using on-chip RAM
RECEIVER 7
Channel 7, Label FF
“
“
“
Channel 7, Label 01
Channel 7, Label 00
RECEIVER 6
Channel 6, Label FF
“
“
“
Channel 6, Label 01
Channel 6, Label 00
Channel 5, Label FF
“
“
“
Channel 5, Label 01
Channel 5, Label 00
RECEIVER 5
8 x ARINC 429
Receive Buses
RECEIVER 4
Channel 4, Label FF
“
“
“
Channel 4, Label 01
Channel 4, Label 00
Channel 3, Label FF
“
“
“
Channel 3, Label 01
Channel 3, Label 00
Channel 2, Label FF
“
“
“
Channel 2, Label 01
Channel 2, Label 00
ARINC 429
RECEIVE
INTERRUPT
TABLE
AINT
AACK
Host CPU
SPI
HCSB
HSCLK
HMOSI
HMISO
RECEIVER 3
RECEIVER 2
RECEIVER 1
Channel 1, Label FF
“
“
“
Channel 1, Label 01
Channel 1, Label 00
Channel 0, Label FF
“
“
“
Channel 0, Label 01
Channel 0, Label 00
RECEIVER 0
8K x 8 RAM
HI-3210
HOLT INTEGRATED CIRCUITS
3
HI-3210
Example 2. ARINC 429 Data reception using on-chip filters and FIFOs
FILTER
TABLE 0
RECEIVER 0
LABEL
FILTER
Message 32
“
“
“
Message 2
Message 1
8 x ARINC 429
Receive Buses
32 x 32 FIFO
SPI
FIFO STATUS
HCSB
HSCLK
HMOSI
HMISO
Host CPU
FIFO EMPTY
FIFO THRESHOLD
FIFO FULL
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
ARINC 429
RECEIVE FIFO
INTERRUPT
CONTROL
AINT
AACK
HI-3210
Example 3. ARINC 429 Data transmission directly from CPU
TRANSMITTER 0
Host CPU
HCSB
HSCLK
HMOSI
HMISO
TRANSMITTER 1
SPI
TRANSMITTER 2
4 x ARINC 429
Transmit Buses
TRANSMITTER 3
HI-3210
Example 4. ARINC 429 Data transmission using on-chip schedulers
Descriptor Table 0
TRANSMIT
SCHEDULER 0
TRANSMITTER 0
Host CPU
HCSB
HSCLK
HMOSI
HMISO
SPI
Descriptor Table 1
TRANSMIT TIMER
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
4 x ARINC 429
Transmit Buses
Descriptor Table 2
Auto-Initialization
EEPROM
ECSB
ESCLK
EMOSI
EMISO
EEPROM
SPI
Descriptor Table 3
RAM
HI-3210
HOLT INTEGRATED CIRCUITS
4
HI-3210
Example 5. Autonomous ARINC 429 Data Concentrator / Repeater
RECEIVER 7
Channel 7, Label FF
“
“
“
Channel 7, Label 01
Channel 7, Label 00
RECEIVER 6
Channel 6, Label FF
“
“
“
Channel 6, Label 01
Channel 6, Label 00
Channel 5, Label FF
“
“
“
Channel 5, Label 01
Channel 5, Label 00
Descriptor Table 3
TRANSMIT
SCHEDULER 3
TRANSMITTER 3
TRANSMIT TIMER
RECEIVER 5
8 x ARINC 429
Receive Buses
RECEIVER 4
Channel 4, Label FF
“
“
“
Channel 4, Label 01
Channel 4, Label 00
Channel 3, Label FF
“
“
“
Channel 3, Label 01
Channel 3, Label 00
Channel 2, Label FF
“
“
“
Channel 2, Label 01
Channel 2, Label 00
Channel 1, Label FF
“
“
“
Channel 1, Label 01
Channel 1, Label 00
Descriptor Table 2
TRANSMIT
SCHEDULER 2
TRANSMITTER 2
4 x ARINC 429
Transmit Buses
TRANSMIT TIMER
RECEIVER 3
Descriptor Table 1
TRANSMIT
SCHEDULER 1
TRANSMITTER 1
RECEIVER 2
TRANSMIT TIMER
RECEIVER 1
Descriptor Table 0
RECEIVER 0
Channel 0, Label FF
“
“
“
Channel 0, Label 01
Channel 0, Label 00
TRANSMIT
SCHEDULER 0
TRANSMITTER 0
TRANSMIT TIMER
EEPROM
SPI
HI-3210
ECSB
ESCLK
EMOSI
EMISO
Auto-Initialization
EEPROM
HOLT INTEGRATED CIRCUITS
5
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