DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD720112
USB 2.0 HUB CONTROLLER
The
µ
PD720112 is a USB 2.0 hub device that complies with the Universal Serial Bus (USB) Specification Revision
2.0 and works up to 480 Mbps. USB 2.0 compliant transceivers are integrated for upstream and all downstream ports.
The
µ
PD720112 works backward compatible either when any one of the downstream ports is connected to a USB 1.1
compliant device, or when the upstream port is connected to a USB 1.1 compliant host.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
µ
PD720112 User’s Manual: S16617E
FEATURES
•
Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)
•
Certified by USB implementers forum and granted the USB 2.0 high-speed Logo
•
High-speed or full-speed packet protocol sequencer for Endpoint 0/1
•
4 (Max.) downstream facing ports
•
All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5
Mbps) transaction.
•
Supports split transaction to handle full-speed and low-speed transaction on downstream facing ports when
Hub controller is working in high-speed mode.
•
One Transaction Translator per Hub and supports four non-periodic buffers
•
Supports self-powered and bus-powered mode
•
Supports Over-current detection and Individual or ganged power control
•
Supports configurable vendor ID, product ID, string descriptors and others with external Serial ROM
•
Supports “non-removable” attribution on individual port
•
Uses 30 MHz X’tal, or clock input
•
Supports downstream port status with LED
•
2.5 V and 3.3 V power supplies
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16616EJ2V0DS00 (2nd edition)
Date Published September 2004 NS CP (N)
Printed in Japan
2004
µ
PD720112
ORDERING INFORMATION
Part Number
Package
80-pin plastic TQFP (Fine pitch) (12
×
12)
µ
PD720112GK-9EU
BLOCK DIAGRAM
To Host/Hub
downstream
facing port
Upstream facing port
UP_PHY
CDR
SERDES
UPC
FS_REP
SIE_2H
ALL_TT
F_TIM
EP1
EP0
CDR
DP(1)_PHY
Downstream facing port #1
DP(2)_PHY
To Hub/Function
upstream facing port
External
Serial ROM
ROM I/F
Downstream facing port #2
DP(3)_PHY
Downstream facing port #3
To Hub/Function
upstream facing port
DPC
To Hub/Function
upstream facing port
APLL
DP(4)_PHY
Downstream facing port #4
To Hub/Function
upstream facing port
X1_CLK/X2
OSB
CSB(4:1)
PPB(4:1)
2
Data Sheet S16616EJ2V0DS
µ
PD720112
APLL
ALL_TT
: Generates all clocks of Hub.
: Translates the high-speed transactions (split transactions) for full/low-speed device
to full/low-speed transactions.
ALL_TT buffers the data transfer from either
upstream or downstream direction. For OUT transaction, ALL_TT buffers data from
upstream port and sends it out to the downstream facing ports after speed
conversion from high-speed to full/low-speed. For IN transaction, ALL_TT buffers
data from downstream ports and sends it out to the upstream facing ports after
speed conversion from full/low-speed to high-speed.
CDR
DPC
DP(n)_PHY
EP0
EP1
F_TIM (Frame Timer)
: Data & clock recovery circuit
: Downstream Port Controller handles Port Reset, Enable, Disable, Suspend and
Resume
: Downstream transceiver supports high-speed (480 Mbps), full-speed (12 Mbps), and
low-speed (1.5 Mbps) transaction
: Endpoint 0 controller
: Endpoint 1 controller
: Manages hub’s synchronization by using micro-SOF which is received at upstream
port, and generates SOF packet when full/low-speed device is attached to
downstream facing port.
FS_REP
OSB
ROM I/F
SERDES
SIE_2H
UP_PHY
UPC
: Full/low-speed repeater is enabled when the
µ
PD720112 are worked at full-speed
mode
: Oscillator Block
: Interface block for external Serial ROM which contains user-defined descriptors
: Serializer and Deserializer
: Serial Interface Engine (SIE) controls USB2.0 and 1.1 protocol sequencer.
: Upstream Transceiver supports high-speed (480 Mbps), full-speed (12 Mbps)
transaction
: Upstream Port Controller handles Suspend and Resume
Data Sheet S16616EJ2V0DS
3
µ
PD720112
PIN CONFIGURATION (TOP VIEW)
•
80-pin plastic TQFP (Fine pitch) (12
×
12)
µ
PD720112GK-9EU
V
SS
V
SS
V
SS
V
DD25
DP4
DM4
V
SS
V
DD25
V
SS
V
DD33
DP3
DM3
V
SS
V
DD33
DP2
DM2
V
SS
V
DD25
DP1
DM1
80
V
DD33
V
DD25
V
SS
V
SS
V
SS
V
DD33
V
SS
V
SS
V
SS
V
SS
V
DD25
V
SS
TEST
SCAN_MODE
BUS_SELF
LPWRM
EXROM_EN
SCL
SDA/GANG_B
V
SS
1
75
70
65
61
60
V
DD33
RPU
V
SS
V
DD25
DPU
DMU
V
SS
V
DD33
V
DD25
V
SS
AV
DD
AV
SS
AV
DD
AV
SS
(R)
RREF
AV
SS
V
DD25
X2
X1_CLK
V
SS
5
55
10
50
15
45
20
21
25
30
35
40
41
4
V
DD33
AMBER
LED4
GREEN
LED3
LED2
LED1
CSB4
V
SS
V
DD25
PPB4
CSB3
PPB3
CSB2
PPB2
CSB1
PPB1
SYSRSTB
VBUSM
V
DD33
Data Sheet S16616EJ2V0DS
µ
PD720112
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
V
DD33
V
DD25
V
SS
V
SS
V
SS
V
DD33
V
SS
V
SS
V
SS
V
SS
V
DD25
V
SS
TEST
SCAN_MODE
BUS_SELF
LPWRM
EXROM_EN
SCL
SDA/GANG_B
V
SS
Pin No.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin Name
V
DD33
AMBER
LED4
GREEN
LED3
LED2
LED1
CSB4
V
SS
V
DD25
PPB4
CSB3
PPB3
CSB2
PPB2
CSB1
PPB1
SYSRSTB
VBUSM
V
DD33
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Pin Name
V
SS
X1_CLK
X2
V
DD25
AV
SS
RREF
AV
SS
(R)
AV
DD
AV
SS
AV
DD
V
SS
V
DD25
V
DD33
V
SS
DMU
DPU
V
DD25
V
SS
RPU
V
DD33
Pin No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin Name
DM1
DP1
V
DD25
V
SS
DM2
DP2
V
DD33
V
SS
DM3
DP3
V
DD33
V
SS
V
DD25
V
SS
DM4
DP4
V
DD25
V
SS
V
SS
V
SS
Remark
AV
SS
(R) should be used to connect RREF through 1 % precision reference resistor of 2.43 kΩ.
Data Sheet S16616EJ2V0DS
5
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