Freescale Semiconductor, Inc.
Addendum
HC908JB16AD/D
Rev. 1, 8/2002
Addendum to
MC68HC908JB16
Technical Data
Freescale Semiconductor, Inc...
This addendum provides update and additional information to the
MC68HC908JB16 Technical Data,
Rev. 1
(Motorola document number MC68HC908JB16/D),
pertaining to the following:
•
MC68HC908JB16
– Update to V
REG
LVI trip point
– 20-pin SOIC package
MC68HC908JB12
MC68HC08JB16
•
•
MC68HC908JB16
This section updates data sheet information and introduces the 20-pin SOIC
package for the MC68HC908JB16.
V
REG
LVI Trip Point
Page 318, entry for minimum V
REG
LVI trip point voltage has been updated.
From:
Characteristic
V
REG
LVI trip point voltage
Symbol
V
LVR
Min
2.0
Typ
2.2
Max
2.6
Unit
V
To:
V
REG
LVI trip point voltage
V
LVR
1.9
2.2
2.6
V
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Freescale Semiconductor, Inc.
HC908JB16AD/D
20-Pin SOIC
Order Number:
MC68HC908JB16JDW
VSS
OSC1
OSC2
VREG
VDD
PTD0/1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RST
Pins not available on 20-pin package:
PTA0/KBA0
PTA1/KBA1
PTA2/KBA2
PTA3/KBA3
PTA4/KBA4
PTA5/KBA5
PTA6/KBA6
PTA7/KBA7
IRQ
PTC1/RxD
PTE0/TCLK
PTE2/T2CH01
PTD2
PTD3
PTD4
PTD5
CGMXFC1
CGMOUT1
VREGA0
VSSA0
CGMXFC2
CGMOUT2
VREGA1
VSSA1
Freescale Semiconductor, Inc...
PTE1/T1CH01
PTE3/D+
PTE4/D–
PTC0/TxD
VDDA
Internal pads are unconnected.
PTD0/1 pin: PTD0 and PTD1 internal pads are bonded together to PTD0/1 pin,
and has 50mA sink capability when configured as an output.
Pin direction must be configured such that DDRD0 = DDRD1.
Figure 1. 20-Pin SOIC Pin Assignment
–A–
20
11
–B–
1
10
10X
P
0.010 (0.25)
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0
_
7
_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0
_
7
_
0.395
0.415
0.010
0.029
20X
D
M
0.010 (0.25)
T A
S
B
J
S
F
R
X 45
_
C
–T–
18X
SEATING
PLANE
G
K
M
Figure 2. 20-Pin SOIC Mechanical Dimensions (Case No. 751D)
Addendum to MC68HC908JB16 Technical Data
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Freescale Semiconductor, Inc.
HC908JB16AD/D
MC68HC908JB12
MC68HC908JB12
This section introduces the MC68HC908JB12, a derivative of the
MC68HC908JB16. The entire MC68HC908JB16 data book, including the
updates in this addendum, applies to this device, with exceptions outlined
below.
Table 1. Summary of MC68HC908JB12 and MC68HC908JB16 Differences
MC68HC908JB12
MC68HC908JB16
16,384 bytes
($BA00–$F9FF)
Available in 32-pin LQFP only.
32-pin LQFP
28-pin SOIC
20-pin SOIC
Freescale Semiconductor, Inc...
FLASH Memory
Dual Clock Generator Module
12,288 bytes
($CA00–$F9FF)
Not implemented.
$0051–$0059 unimplemented.
—
28-pin SOIC
20-pin SOIC
Available Packages
(1)
Notes:
1. The pin assignments are identical for both devices; see data sheet.
MCU Block Diagram
Figure 3
shows the structure of the MC68HC908JB12.
Memory Map
Figure 4
shows the memory map of the MC68HC908JB12.
Dual Clock
Generator Module
The dual 27-MHz clock generator module on the MC68HC908JB16 is not
designed in the MC68HC908JB12, hence, register locations from $0051 to
$0059 are unimplemented. Information in the data book relating to the CGM do
not apply to the MC68HC908JB12.
Addendum to MC68HC908JB16 Technical Data
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INTERNAL BUS
M68HC08 CPU
ARITHMETIC/LOGIC
UNIT (ALU)
DDRA
KEYBOARD INTERRUPT
MODULE
PTA
(3)
HC908JB16AD/D
CPU
REGISTERS
PTA7/KBA7
:
PTA0/KBA0
CONTROL AND STATUS REGISTERS — 128 BYTES
BREAK
MODULE
USER FLASH MEMORY — 12,288 BYTES
DDRC
PTC
SERIAL COMMUNICATIONS
INTERFACE MODULE
LOW VOLTAGE INHIBIT
MODULE
PTD5
(4), (6)
PTD4
(4), (6)
PTD
PTD3
(4), (6)
DDRD
PTD2
(4), (6)
PTD1
(4), (7)
PTD0
(4), (7)
PTC1/RxD
(3), (6)
PTC0/TxD
(3)
USER RAM — 384 BYTES
MONITOR ROM — 1,472 BYTES
POWER-ON RESET
MODULE
USER FLASH VECTORS — 48 BYTES
(1)
(1)
OSC1
OSC2
OSCILLATOR
COMPUTER OPERATING
PROPERLY MODULE
2-CHANNEL TIMER INTERFACE
MODULE 1
2-CHANNEL TIMER INTERFACE
MODULE 2
SYSTEM INTEGRATION
MODULE
PTE4/D–
(3), (4)
PTE3/D+
DDRE
PTE
(3), (4)
(2)
RST
USB MODULE
USB ENDPOINT 0, 1, 2
PTE2/T2CH01
(3), (6)
PTE1/T1CH01
(3)
PTE0/TCLK
(3), (6)
Addendum to MC68HC908JB16 Technical Data
LS USB
TRANSCEIVER
IRQ
MODULE
POWER AND INTERNAL
VOLTAGE REGULATORS
(1) Pins have 3V logic.
(2) Pins have integrated pullup device.
(3) Pins have software configurable pullup device.
(4) Pins are open-drain when configured as output.
Freescale Semiconductor, Inc.
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(3)
IRQ
V
DD
V
SS
V
REG
(3.3V)
(6) Pins available on 28-pin package only.
(7) On 20-pin package, PTD0 and PTD1 are bonded as a single PTD0/1 pin.
Figure 3. MC68HC908JB12 Block Diagram
Freescale Semiconductor, Inc.
HC908JB16AD/D
MC68HC908JB12
$0000
↓
$007F
$0080
↓
$01FF
$0200
↓
$C9FF
$CA00
↓
$F9FF
$FA00
↓
$FDFF
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
$FE0E
$FE0F
$FE10
↓
$FFCF
$FFD0
↓
$FFFF
I/O Registers
128 Bytes
RAM
384 Bytes
Unimplemented
51,200 Bytes
FLASH Memory
12,288 Bytes
Monitor ROM 1
1,024 Bytes
SIM Break Status Register (SBSR)
SIM Reset Status Register (SRSR)
Reserved
SIM Break Flag Control Register (SBFCR)
Interrupt Status Register 1 (INT1)
Interrupt Status Register 2 (INT2)
Reserved
Reserved
FLASH Control Register (FLCR)
FLASH Block Protect Register (FLBPR)
Reserved
Reserved
Break Address Register High (BRKH)
Break Address Register Low (BRKL)
Break Status and Control Register (BRKSCR)
Reserved
Monitor ROM 2
448 Bytes
FLASH Vectors
48 Bytes
Freescale Semiconductor, Inc...
Figure 4. MC68HC908JB12 Memory Map
Addendum to MC68HC908JB16 Technical Data
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