Technical Data Reference Guide
netX 500/100
next Generation of Communication Controllers
Hilscher Gesellschaft für Systemautomation mbH
www.hilscher.com
DOC061102TRG15EN | Revision 1.5 | English | 2015-07 | Released | Public
Table of Contents
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Table of Contents
1
1.1
1.2
1.3
INTRODUCTION
Product Features
Differences netX 500 – netX 100
Typical Applications
5
7
8
8
2
FUNCTIONAL OVERVIEW
9
9
9
10
12
13
14
15
15
16
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17
28
33
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34
35
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55
57
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61
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67
68
68
69
72
73
73
2.1
CPU
2.2
Oscillator
2.3
System LED and Boot Modes
2.4
Extended System Information
2.5
Reset
2.6
Reset Configuration
2.7
Watchdog
2.7.1
WDGACT Signal
2.8
Internal Memory
2.9
External Memory
2.9.1
SRAM / FLASH Interface
2.9.2
SDRAM
2.10
Extension Bus
2.10.1 Extension Bus Configuration
2.10.2 Extension Bus Address Space and netX Memory Allocation
2.10.3 Address and Data Byte Steering
2.10.4 Intel / Motorola Data Format
2.10.5 Multiplexed / Non-Multiplexed Data Bus
2.10.6 Data Ready or Data Acknowledge
2.10.7 End-Of-Cycle
2.10.8 Pin Description of Extension Bus
2.10.9 Extension Bus Component Connection
2.10.10
Extension Bus Timing without Wait-states
2.10.11
Extension Bus Timing with Waitstates
2.11
Dual-Port memory
2.11.1 Dual-Port Memory Interface Mode
2.11.2 Dual-Port Memory Structure and Allocation
2.11.3 Global Control Block
2.11.4 DPM interface signals
2.11.5 Interrupts and Interrupt Signal
2.11.6 Dual-Port Memory Timing
2.12
Timer
2.13
Real-time clock and Backup RAM
2.14
IEEE 1588 System Time
2.15
JTAG Debug Interface
2.15.1 Standard JTAG connector
2.15.2 Hilscher “mini-JTAG” Connector
2.15.3 Boundary Scan mode
2.16
Embedded Trace Macrocell ETM
2.17
Vectored Interrupt Controller
2.17.1 Interrupt generation
2.17.2 Interrupt priority logic
2.17.3 Interrupt flow sequence
2.18
UART
2.19
USB
2.20
I2C
2.21
SPI
netX 500/100 | Technical Data Reference Guide
DOC061102TRG15EN | Revision 1.5 | English | 2015-07 | Released | Public
© Hilscher, 2006-2015
Table of Contents
2.22
2.23
2.24
2.25
2.25.1
2.25.2
2.25.3
2.25.4
2.26
2.26.1
2.27
2.27.1
2.27.2
2.27.3
2.27.4
2.27.5
2.28
GPIO
PIO
LCD
Motion Control Functions
AD-Converter
Motor PWM
Resolver PWM
Encoder interface
Ethernet Interface
Real Time Ethernet
Fieldbus Interface
AS interface Master
CANopen Interface
CC-Link Interface
DeviceNet Interface
PROFIBUS Interface
XMAC Resource Sharing
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3
3.1
3.2
ETHERNET COMMUNICATION STRUCTURE
Ethernet data transfer
Error Counters
94
95
96
4
INTERNAL ROM
97
97
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97
97
98
99
100
100
102
103
103
103
103
103
103
4.1
Boot Function
4.1.1
The 1
st
Stage Bootstrap
4.1.2
The 2
nd
Stage Bootstrap
4.1.3
The Application Code
4.1.4
The general Bootstrap Sequence.
4.1.5
The 1
st
Stage Bootstrap Options
4.1.6
The 1
st
Stage Boot Option Selection
4.1.7
The 1
st
Stage Boot Option detection
4.2
High Performance Real-Time Operating System rcX
4.2.1
Pre-emptive Kernel
4.2.2
Small Footprint
4.2.3
Modularity
4.2.4
Dynamic Objects
4.2.5
Rich API Functions
4.2.6
Tool Support
5
ELECTRICAL SPECIFICATIONS
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104
105
106
108
108
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© Hilscher, 2006-2015
5.1
Absolute Maximum Ratings
5.2
Power Up Sequencing
5.3
Power Consumption / Power Dissipation
5.4
AC / DC Specifications
5.4.1
DC Parameters
5.4.2
System Oscillator
5.4.3
RTC Oscillator
5.4.4
Power On Reset / Reset Input
5.4.5
USB
5.4.6
ADC
5.4.7
PHY
5.4.8
SDRAM
5.4.9
SRAM / FLASH
5.4.10 SPI
5.4.11 I
2
C
5.4.12 UART
5.4.13 Dual-port memory
5.4.14 Extension bus
5.4.15 LCD
5.4.16 JTAG
netX 500/100 | Technical Data Reference Guide
DOC061102TRG15EN | Revision 1.5 | English | 2015-07 | Released | Public
Table of Contents
5.4.17 Fieldbus / PWM / Encoder
5.5
Failure Rate (FIT)
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135
136
6
PACKAGE INFORMATION
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147
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6.1
Package Thermal Specification
6.2
Soldering Conditions
6.2.1
Infrared Reflow Soldering Characterization
6.2.2
Vapour Phase Reflow Soldering (VPS) Characterization
6.3
General storage conditions
6.4
Signal Definitions
6.4.1
Schematic View of netX Pad Types
6.5
Pin Table Sorted By Pin Numbers
6.6
Pin Table Sorted By Signals
6.7
Pin Overview
6.8
Device Marking
6.8.1
netX 100
6.8.2
netX 500
6.9
Mechanical Dimensions / Physical Dimensions
6.10
Material composition
6.10.1 Solder balls
6.11
Ordering Information
6.12
Packing
7
7.1
7.2
7.3
PRINTED CIRCUIT BOARD DESIGN
netX Trace Wiring
V
cc
Pin Requirements / Decoupling Capacitors
Reference PCB Layout Design
158
159
160
161
8
8.1
REFERENCE SCHEMATICS
Bill of Materials of Reference Design
162
179
9
10
REVISION HISTORY
CONTACTS
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netX 500/100 | Technical Data Reference Guide
DOC061102TRG15EN | Revision 1.5 | English | 2015-07 | Released | Public
© Hilscher, 2006-2015
Introduction
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1
Introduction
Slave
Data Switch
netX 500 Block diagram
The netX 500 is a highly integrated network controller with a new system architecture optimized for
communication and maximum data throughput.
Based on the 32-Bit CPU ARM 926EJ-S clocked with 200 MHz, it provides a memory management unit,
16K instruction- and 8K data caches, 8K tightly coupled data memory and DSP- and Java extensions.
Together with 32 Kbytes ROM holding the boot loader and a Real-Time kernel, the internal memory of
144 Kbytes RAM is sufficient for smaller applications, while 16K of the internal RAM can be buffered by
a separate (battery-) power supply for storing non volatile data.
The connection to a primary host is accomplished by the dual-port memory mode of the host interface,
which is also configurable as a 16 Bit extension bus for stand-alone applications. Comprehensive pe-
ripheral functions and serial interfaces such as UARTs, USB, SPI and I²C provide a wide spectrum of
applications. Yet, it is the central data switch and the four freely configurable communication channels
with their own intelligence that are the main characteristics of the netX as a "high end” network control-
ler.
The data switch interconnects the ARM CPU, communication and Host controllers, memory blocks and
peripheral units via five data paths. This allows the controllers to transmit their data in parallel, contrary
to the traditional sequential architecture with only one common data bus and additional bus arbitration
cycles. To allow efficient use of the data switch, the internal SRAM is divided in five separate blocks (4 *
32K and 1* 16K) that can be accessed individually (for instance, the ARM CPU can access one block of
the internal SRAM, while, at the same time, the Host Controller and an xPEC can read from or write to
the other three memory blocks).
netX 500/100 | Technical Data Reference Guide
DOC061102TRG15EN | Revision 1.5 | English | 2015-07 | Released | Public
© Hilscher, 2006-2015
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Slave
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