GTL2002
2-bit bidirectional low voltage translator
Rev. 07 — 2 July 2009
Product data sheet
1. General description
The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide
high-speed voltage translation with low ON-state resistance and minimal propagation
delay. The GTL2002 provides 2 NMOS pass transistors (Sn and Dn) with a common gate
(GREF) and a reference transistor (SREF and DREF). The device allows bidirectional
voltage translations between 1.0 V and 5.0 V without use of a direction pin.
When the Sn or Dn port is LOW the clamp is in the ON-state and a low resistance
connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn
port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by
the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to V
CC
by
the pull-up resistors. This functionality allows a seamless translation between higher and
lower voltages selected by the user, without the need for directional control.
All transistors have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the transistors is
symmetrical. Because all transistors in the device are identical, SREF and DREF can be
located on any of the other two matched Sn/Dn transistors, allowing for easier board
layout. The translator's transistors provide excellent ESD protection to lower voltage
devices and at the same time protect less ESD-resistant devices.
2. Features
I
2-bit bidirectional low voltage translator
I
Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5 V
buses, which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels
I
Provides bidirectional voltage translation with no direction pin
I
Low 6.5
Ω
ON-state resistance (R
on
) between input and output pins (Sn/Dn)
I
Supports hot insertion
I
No power supply required; will not latch up
I
5 V tolerant inputs
I
Low standby current
I
Flow-through pinout for ease of printed-circuit board trace routing
I
ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Packages offered: SO8, TSSOP8 (MSOP8), VSSOP8, XQFN8U
NXP Semiconductors
GTL2002
2-bit bidirectional low voltage translator
3. Applications
I
Any application that requires bidirectional or unidirectional voltage level translation
from any voltage between 1.0 V and 5.0 V to any voltage between 1.0 V and 5.0 V
I
The open-drain construction with no direction pin is ideal for bidirectional low voltage
(e.g., 1.0 V, 1.2 V, 1.5 V, or 1.8 V) processor I
2
C-bus port translation to the normal
3.3 V or 5.0 V I
2
C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal
levels.
4. Ordering information
Table 1.
Ordering information
Package
Name
GTL2002D
GTL2002DP
GTL2002DP/Q900
[2]
GTL2002DC
GTL2002GM
SO8
TSSOP8
[1]
TSSOP8
[1]
VSSOP8
XQFN8U
Description
plastic small outline package; 8 leads; body width 3.9 mm
plastic thin shrink small outline package; 8 leads; body width 3 mm
plastic thin shrink small outline package; 8 leads; body width 3 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic extremely thin quad flat package; no leads; 8 terminals;
UTLP based; body 1.6
×
1.6
×
0.5 mm
Version
SOT96-1
SOT505-1
SOT505-1
SOT765-1
SOT902-1
Type number
[1]
[2]
Also known as MSOP8.
GTL2002DP/Q900 is AEC-Q100 compliant. Contact
i2c.support@nxp.com
for PPAP.
4.1 Ordering options
Table 2.
GTL2002D
GTL2002DP
GTL2002DP/Q900
GTL2002DC
GTL2002GM
[1]
Ordering options
Topside mark
GTL2002
2002
2002
2002
G2X
[1]
Temperature range
T
amb
=
−40 °C
to +85
°C
T
amb
=
−40 °C
to +85
°C
T
amb
=
−40 °C
to +85
°C
T
amb
=
−40 °C
to +85
°C
T
amb
=
−40 °C
to +85
°C
Type number
‘X’ will change based on date code.
GTL2002_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 2 July 2009
2 of 22
NXP Semiconductors
GTL2002
2-bit bidirectional low voltage translator
5. Functional diagram
DREF
GREF
D1
D2
SREF
S1
S2
002aac784
Fig 1.
Functional diagram
6. Pinning information
6.1 Pinning
GTL2002DP
GTL2002DP/Q900
GND
SREF
S1
S2
1
2
8
7
GREF
GND
DREF
D1
D2
1
2
3
4
002aac778
8
7
6
5
GREF
DREF
D1
D2
GTL2002D
3
4
002aac777
SREF
S1
S2
6
5
Fig 2.
Pin configuration for SO8
Fig 3.
Pin configuration for TSSOP8
(MSOP8)
GREF
1
8
terminal 1
index area
GND
7
DREF
GTL2002GM
SREF
SREF
S1
S2
GND
1
2
3
4
002aac779
2
6
D1
8
GREF
4
DREF
D1
D2
S2
002aac780
GTL2002DC
7
6
5
S1
3
5
D2
Transparent top view
Fig 4.
Pin configuration for VSSOP8
Fig 5.
Pin configuration for XQFN8U
GTL2002_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 2 July 2009
3 of 22
NXP Semiconductors
GTL2002
2-bit bidirectional low voltage translator
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SO8, TSSOP8, VSSOP8
XQFN8U
GND
SREF
S1
S2
D2
D1
DREF
GREF
1
2
3
4
5
6
7
8
4
1
2
3
5
6
7
8
ground (0 V)
source of reference transistor
port S1
port S2
port D2
port D1
drain of reference transistor
gate of reference transistor
Description
7. Functional description
Refer to
Figure 1 “Functional diagram”.
7.1 Function selection
Table 4.
Function selection, HIGH to LOW translation
Assuming Dn is at the higher voltage level.
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
GREF
[1]
H
H
H
L
[1]
[2]
[3]
[4]
DREF
H
H
H
L
SREF
0V
V
TT[4]
V
TT[4]
0 V
−
V
TT[4]
Input Dn
X
H
L
X
Output Sn
X
V
TT[2][4]
L
[3]
X
Transistor
off
on
on
off
GREF should be at least 1.5 V higher than SREF for best translator operation.
Sn is not pulled up or pulled down.
Sn follows the Dn input LOW.
V
TT
is equal to the SREF voltage.
Table 5.
Function selection, LOW to HIGH translation
Assuming Dn is at the higher voltage level.
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
GREF
[1]
H
H
H
L
[1]
[2]
[3]
[4]
GTL2002_7
DREF
H
H
H
L
SREF
0V
V
TT[4]
V
TT[4]
0 V
−
V
TT[4]
Input Sn
X
V
TT[4]
L
X
Output Dn
X
H
[2]
L
[3]
X
Transistor
off
nearly off
on
off
GREF should be at least 1.5 V higher than SREF for best translator operation.
Dn is pulled up to V
CC
through an external resistor.
Dn follows the Sn input LOW.
V
TT
is equal to the SREF voltage.
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 2 July 2009
4 of 22
NXP Semiconductors
GTL2002
2-bit bidirectional low voltage translator
8. Application design-in information
8.1 Bidirectional translation
For the bidirectional clamping configuration, higher voltage to lower voltage or lower
voltage to higher voltage, the GREF input must be connected to DREF and both pins
pulled to HIGH side V
CC
through a pull-up resistor (typically 200 kΩ). A filter capacitor on
DREF is recommended. The processor output can be totem pole or open-drain (pull-up
resistors may be required) and the chip set output can be totem pole or open-drain
(pull-up resistors are required to pull the Dn outputs to V
CC
). However, if either output is
totem pole, data must be unidirectional or the outputs must be 3-stateable and the outputs
must be controlled by some direction control mechanism to prevent HIGH-to-LOW
contentions in either direction. If both outputs are open-drain, no direction control is
needed. The opposite side of the reference transistor (SREF) is connected to the
processor core power supply voltage. When DREF is connected through a 200 kΩ resistor
to a 3.3 V to 5.5 V V
CC
supply and SREF is set between 1.0 V to (V
CC
−
1.5 V), the output
of each Sn has a maximum output voltage equal to SREF and the output of each Dn has
a maximum output voltage equal to V
CC
.
1.8 V
1.5 V
1.2 V
1.0 V
GND
V
CORE
CPU I/O
S2
SREF
S1
5V
200 kΩ
totem pole or
open-drain I/O
GREF
DREF
D1
CHIPSET I/O
D2
V
CC
increase bit size
by using 10-bit GTL2010
or 22-bit GTL2000
V
CC
S3
S4
S5
Sn
D3
3.3 V
CHIPSET I/O
D4
D5
Dn
002aac060
Typical bidirectional voltage translation.
Fig 6.
Bidirectional translation to multiple higher voltage levels such as an I
2
C-bus
application
GTL2002_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 2 July 2009
5 of 22
stm32/stm8
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