SSM3J328R
TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type (U-MOSⅥ)
SSM3J328R
○
Power Management Switch Applications
•
•
1.5-V drive
Low ON-resistance: R
DS(ON)
= 88.4mΩ
R
DS(ON)
= 56.0mΩ
R
DS(ON)
= 39.7mΩ
R
DS(ON)
= 29.8mΩ
(max) (@V
GS
= -1.5 V)
(max) (@V
GS
= -1.8 V)
(max) (@V
GS
= -2.5 V)
(max) (@V
GS
= -4.5 V)
0.05 M A
0.42
-0.05
3
+0.08
Unit: mm
0.17
-0.07
+0.08
1.8±0.1
Absolute Maximum Ratings
(Ta = 25°C)
Characteristic
Drain-source voltage
Gate-source voltage
Drain current
Power dissipation
Channel temperature
Storage temperature range
DC
Pulse
Symbol
V
DSS
V
GSS
I
D
(Note 1)
I
DP
(Note 1,2)
P
D
(Note 3)
t = 10s
T
ch
T
stg
Rating
-20
±
8
-6.0
-24.0
1
2
150
−55
to 150
Unit
V
V
A
1
2
0.95
0.95
2.9±0.2
2.4±0.1
A
1: Gate
W
°C
°C
2: Source
3: Drain
SOT-23F
JEDEC
―
Note: Using continuously under heavy loads (e.g. the application of high
temperature/current/voltage and the significant change in
JEITA
―
temperature, etc.) may cause this product to decrease in the
TOSHIBA
2-3Z1A
reliability significantly even if the operating conditions (i.e.
operating temperature/current/voltage, etc.) are within the
Weight: 11 mg (typ.)
absolute maximum ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: The channel temperature should not exceed 150°C during use.
Note 2: PW
≤
10μs,Duty
≤
1％
Note 3: Mounted on a FR4 board.
2
(25.4 mm
×
25.4 mm
×
1.6 mm, Cu Pad: 645 mm )
Marking
3
Equivalent Circuit (Top view)
3
KFH
1
2
1
2
Start of commercial production
2010-08
1
2014-03-01
0.8
+0.08
-0.05
SSM3J328R
Electrical Characteristics
(Ta = 25°C)
Characteristic
Drain-source breakdown voltage
Drain cut-off current
Gate leakage current
Gate threshold voltage
Forward transfer admittance
Symbol
Test Conditions
Min
-20
(Note 5)
-15
⎯
⎯
-0.3
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
4.5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
(Note 4)
⎯
Typ.
⎯
⎯
⎯
⎯
⎯
9.1
24.9
31.1
38.8
47.4
840
118
99
12.8
1.4
3.0
32
107
0.87
Max
⎯
⎯
-1
±1
-1.0
⎯
29.8
39.7
56.0
88.4
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
1.2
ns
V
nC
pF
mΩ
Unit
V
V
μA
μA
V
S
V
(BR) DSS
I
D
= -1 mA, V
GS
= 0 V
V
(BR) DSX
I
D
= -1 mA, V
GS
= 5 V
I
DSS
I
GSS
V
th
⏐Y
fs
⏐
V
DS
= -20 V, V
GS
= 0 V
V
GS
=
±8
V, V
DS
= 0 V
V
DS
= -3 V, I
D
= -1 mA
V
DS
= -3 V, I
D
= -1.0 A
I
D
= -3.0 A, V
GS
= -4.5 V
Drain–source ON-resistance
R
DS (ON)
I
D
= -2.5 A, V
GS
= -2.5 V
I
D
= -1.5 A, V
GS
= -1.8 V
I
D
= -0.5 A, V
GS
= -1.5 V
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Switching time
Turn-on time
Turn-off time
C
iss
C
oss
C
rss
Q
g
Q
gs1
Q
gd
t
on
t
off
V
DSF
V
DS
= -10 V, V
GS
= 0 V
f = 1 MHz
V
DD
= -10 V, I
DS
= -4.0 A,
V
GS
= -4.5 V
V
DD
= -10 V, I
D
= -2.0 A
V
GS
= 0 to -2.5 V, R
G
= 4.7
Ω
I
D
= 6.0 A, V
GS
= 0 V
Drain-Source forward voltage
Note4: Pulse test
Note5: If a forward bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the
drain-source breakdown voltage is lowered in this mode.
Switching Time Test Circuit
(a) Test Circuit
(b) V
IN
0
OUT
IN
−2.5
V
R
G
R
L
V
DD
V
DD
t
on
10%
0V
90%
−
2.5V
10
μs
(c) V
OUT
V
DS (ON)
90%
10%
t
r
t
off
t
f
V
DD
= -10 V
R
G
= 4.7
Ω
Duty
≤
1%
V
IN
: t
r
, t
f
< 5 ns
Common Source
Ta = 25°C
Notice on Usage
Let V
th
be the voltage applied between gate and source that causes the drain current (I
D
) to be low (-1 mA for the
SSM3J328R). Then, for normal switching operation, V
GS(on)
must be higher than V
th,
and V
GS(off)
must be lower than
V
th.
This relationship can be expressed as: V
GS(off)
< V
th
< V
GS(on)
.
Take this into consideration when using the device.
Handling Precaution
When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is
protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that
come into direct contact with devices should be made of antistatic materials.
Thermal resistance R
th (ch-a)
and power dissipation P
D
vary depending on board material, board area, board thickness
and pad area. When using this device, please take heat dissipation into consideration.
2
2014-03-01
SSM3J328R
I
D
– V
DS
-10
VGS
=-4.5
V
-8
-1.5 V
-6
-2.5 V
-1.8 V
-100
Common Source
VDS
=
-3 V
Pulse test
I
D
– V
GS
-10
(A)
(A)
Drain current
I
D
-1
-0.1
Ta
=
100 °C
-0.01
−25
°C
-0.001
Drain current
I
D
-4
-2
0
Common Source
Ta
=
25 °C
Pulse test
0
-0.2
-0.4
-0.6
-0.8
-1
25 °C
-0.0001
0
-0.5
-1.0
-1.5
-2.0
Drain–source voltage
V
DS
(V)
Gate–source voltage
V
GS
(V)
R
DS (ON)
– V
GS
140
120
ID =-0.5A
Common Source
Pulse test
140
120
R
DS (ON)
– V
GS
ID =-2.5A
Common Source
Pulse test
Drain–source ON-resistance
R
DS (ON)
(mΩ)
100
80
60
40
Ta
=
100 °C
25 °C
Drain–source ON-resistance
R
DS (ON)
(mΩ)
100
80
60
25 °C
40
Ta
=
100 °C
20
0
−
25 °C
0
-2
-4
-6
-8
20
−
25 °C
0
0
-2
-4
-6
-8
Gate–source voltage
V
GS
(V)
Gate–source voltage
V
GS
(V)
R
DS (ON)
– I
D
140
120
140
Common Source
Ta = 25°C
-1.5 V
120
Common Source
Pulse test
R
DS (ON)
– Ta
Drain–source ON-resistance
R
DS (ON)
(mΩ)
Drain–source ON-resistance
R
DS (ON)
(mΩ)
Pulse test
100
80
100
-1.5 A / -1.8 V
-2.5 A / -2.5 V
ID
=
-0.5 A / VGS
=
-1.5 V
80
60
40
60
40
20
-2.5 V
0
0
-2.0
-4.0
-6.0
-1.8 V
-4.5 V
20
0
−50
-3.0 A / -4.5 V
-8.0
-10.0
0
50
100
150
Drain current
I
D
(A)
Ambient temperature
Ta
(°C)
3
2014-03-01
SSM3J328R
V
th
– Ta
Common Source
VDS = -3 V
ID = -1 mA
(S)
-1.0
|Y
fs
| – I
D
100
Common Source
30
VDS
=
-3 V
Ta
=
25 °C
Pluse test
V
th
(V)
-0.8
Forward transfer admittance
⎪Y
fs
⎪
Gate threshold voltage
10
-0.6
3.0
-0.4
1.0
-0.2
0.3
0
−50
0
50
100
150
0.1
-0.01
-0.1
-1
-10
-100
Ambient temperature
Ta
(°C)
Drain current
I
D
(A)
10000
5000
C – V
DS
-8
Dynamic Input Characteristic
(pF)
3000
Ciss
(V)
-6
1000
500
300
V
GS
C
VDD
=
-10 V
VDD
=
-16 V
Capacitance
Gate–source voltage
-4
100
50
30
Common Source
Ta
=
25 °C
f
=
1 MHz
VGS
=
0 V
-1
-10
Coss
Crss
-2
Common Source
ID
=
-4.0 A
Ta
=
25 °C
0
0
10
20
30
10
-0.1
-100
Drain–source voltage
V
DS
(V)
Total Gate Charge
Qg
(nC)
10000
toff
tf
t – I
D
Common Source
VDD = -10 V
VGS = 0 to -2.5 V
Ta = 25 °C
RG = 4.7Ω
I
DR
– V
DS
100
Common Source
VGS
=
0 V
Ta
=
25 °C
D
Pulse test
I
DR
G
1
(A)
I
DR
10
(ns)
1000
100
Drain reverse current
S
Switching time
t
0.1
ton
10
tr
0.01
100 °C
0.001
0
25 °C
−25
°C
0.4
0.6
0.8
1.0
1.2
1
-0.001
-0.01
-0.1
-1
-10
0.2
Drain current
I
D
(A)
Drain–source voltage
V
DS
(V)
4
2014-03-01
SSM3J328R
R
th
1000
–
t
w
1600
a: Mounted on FR4 board
b
P
D
– Ta
(25.4mm
×
25.4mm
×
1.6mm , Cu Pad : 645 mm
2
)
b: Mounted on FR4 board
(25.4mm
×
25.4mm
×
1.6mm , Cu Pad : 0.72 mm
2
×3)
(°C/W )
(mW)
R
th
a
100
1200
a
Transient thermal impedance
P
D
10
Single pulse
a. Mounted on FR4 board
(25.4 mm
×
25.4 mm
×
1.6 mm, Cu Pad: 645 mm
2
)
b. Mounted on FR4 board
(25.4 mm
×
25.4 mm
×
1.6 mm, Cu Pad: 0.72 mm
2
×3)
Power dissipation
800
400
b
1
0.001
0.01
0.1
1
10
100
1000
0
-40
-20
0
20
40
60
80
100
120
140
160
Pulse width
t
w
(s)
Ambient temperature
Ta
(°C)
5
2014-03-01
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