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SSM3K131TU

产品描述TOSHIBA Field-Effect Transistor Silicon N-Channel MOS Type (U-MOIV)
文件大小196KB,共6页
制造商Toshiba(东芝)
官网地址http://toshiba-semicon-storage.com/
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SSM3K131TU概述

TOSHIBA Field-Effect Transistor Silicon N-Channel MOS Type (U-MOIV)

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SSM3K131TU
TOSHIBA Field-Effect Transistor Silicon N-Channel MOS Type (U-MOSⅣ)
SSM3K131TU
High-Speed Switching Applications
4.5-V drive
Low ON-resistance : R
on
= 41.5 mΩ (max) (@V
GS
= 4.5 V)
: R
on
= 27.6 mΩ (max) (@V
GS
= 10 V)
0.65±0.05
Unit: mm
2.1±0.1
1.7±0.1
+0.1
0.3 -0.05
3
0.166±0.05
1: Gate
2: Source
3: Drain
Typ.
23.0
20.5
27.0
450
120
77
10.1
7.6
2.5
21
15
-0.85
Max
1
±0.1
2.5
27.6
41.5
-1.2
ns
V
nC
pF
Unit
V
μA
μA
V
S
Absolute Maximum Ratings
(Ta = 25°C)
Characteristic
Drain-Source voltage
Gate-Source voltage
Drain current
DC
Pulse
I
D
Symbol
V
DSS
V
GSS
(Note 1)
I
DP
(Note 1)
P
D
(Note 2)
Drain power dissipation
P
D
(Note 3)
t = 10 s
Channel temperature
Storage temperature range
T
ch
T
stg
Rating
30
±20
6.0
12.0
800
500
1000
150
−55
to 150
°C
°C
mW
Unit
V
V
2.0±0.1
1
2
Using continuously under heavy loads (e.g. the application of high
temperature/current/voltage and the significant change in temperature,
etc.) may cause this product to decrease in the reliability significantly
JEDEC
even if the operating conditions (i.e. operating temperature/current/
voltage, etc.) are within the absolute maximum ratings.
JEITA
Please design the appropriate reliability upon reviewing the Toshiba
TOSHIBA
2-2U1A
Semiconductor Reliability Handbook (“Handling Precautions”/“Derating
Concept and Methods”) and individual reliability data (i.e. reliability test
Weight: 6.6mg (typ.)
report and estimated failure rate, etc).
Note 1: The junction temperature should not exceed 150°C during use.
2
Note 2: Mounted on a ceramic board. (25.4 mm
×
25.4 mm
×
0.8 mm, Cu Pad: 645 mm )
2
Note 3: Mounted on an FR4 board. (25.4 mm
×
25.4 mm
×
1.6 mm, Cu Pad: 645 mm )
Note:
UFM
Electrical Characteristics
(Ta = 25°C)
Characteristic
Drain-Source breakdown voltage
Drain cut-off current
Gate leakage current
Gate threshold voltage
Forward transfer admittance
Drain–source ON-resistance
Input capacitance
Output capacitance
Reverse transfer capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Switching time
Turn-on time
Turn-off time
Symbol
V
(BR) DSS
V
(BR) DSX
I
DSS
I
GSS
V
th
⏐Y
fs
R
DS (ON)
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
t
on
t
off
V
DSF
V
DS
= 15 V, I
D
= 6.0 A
V
GS
= 10 V
V
DD
=
15 V, I
D
=
2.0 A,
V
GS
=
0 to 4.5 V, R
G
=
10
Ω
I
D
=
-6.0 A, V
GS
=
0 V
(Note 4)
V
DS
=
15 V, V
GS
=
0 V, f
=
1 MHz
Test Conditions
I
D
=
10 mA, V
GS
=
0 V
I
D
=
10 mA, V
GS
=
-20 V
V
DS
=
30 V, V
GS
=
0 V
V
GS
= ±
20 V, V
DS
=
0 V
V
DS
=
5 V, I
D
=
1 mA
V
DS
=
5 V, I
D
=
4 A
I
D
=
4.0 A, V
GS
=
10 V
I
D
=
2.0 A, V
GS
=
4.5 V
(Note 4)
(Note 4)
(Note 4)
Min
30
15
1.3
11.5
Drain-Source forward voltage
Note 4: Pulse test
Start of commercial production
0.7±0.05
A
2008-09
1
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