Three-state outputs drive bus lines or buffer memory address
registers
• 1.2µ
radiation-hardened CMOS
- Latchup immune
•
High speed
•
Low power consumption
•
Single 5 volt supply
•
Available QML Q or V processes
•
Flexible package
- 20-pin DIP
- 20-lead flatpack
DESCRIPTION
The UT54ACS541 and the UT54ACTS541 are non-inverting
octal buffers and line drivers which improve the performance
and density of three-state memory address drivers, clock drivers,
and bus-oriented receivers and transmitters.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
1G
L
L
H
X
2G
L
L
X
H
An
L
H
X
X
OUTPUT
Yn
L
H
Z
Z
PINOUTS
20-Pin DIP
Top View
1G
A1
A2
A3
A4
A5
A6
A7
A8
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
2G
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
20-Lead Flatpack
Top View
1G
A1
A2
A3
A4
A5
A6
A7
A8
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
2G
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
LOGIC SYMBOL
1G
2G
(1)
(19)
&
EN
A1 (2)
(3)
A2
A3 (4)
(5)
A4
A5 (6)
A6 (7)
A7 (8)
A8 (9)
(18)
Y1
(17)
Y2
(16) Y3
(15)
(14)
(13)
(12)
(11)
Y4
Y5
Y6
Y7
Y8
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
235
RadHard MSI Logic
UT54ACS541/UT54ACTS541
LOGIC DIAGRAM
A8
(9)
A7
(8)
A6
(7)
A5
(6)
A4
(5)
A3
(4)
A2
(3)
A1
2G 1G
(1)
(2) (19)
(11)
Y8
(12)
Y7
(13)
Y6
(14)
Y5
(15)
Y4
(16)
Y3
(17)
Y2
(18)
Y1
RADIATION HARDNESS SPECIFICATIONS
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
20
±10
1
UNITS
V
V
°C
°C
°C
°C/W
mA
W
RadHard MSI Logic
236
UT54ACS541/UT54ACTS541
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
°C
237
RadHard MSI Logic
UT54ACS541/UT54ACTS541
DC ELECTRICAL CHARACTERISTICS
7
(V
DD
= 5.0V
±
10%; V
SS
= 0V
6
, -55°C < T
C
< +125°C)
SYMBOL
V
IL
PARAMETER
Low-level input voltage
1
ACTS
ACS
High-level input voltage
1
ACTS
ACS
Input leakage current
ACTS/ACS
Low-level output voltage
3
ACTS
ACS
High-level output voltage
3
ACTS
ACS
Three-state output leakage current
Short-circuit output current
2 ,4
ACTS/ACS
Output current
10
(Sink)
I
OH
Output current
10
(Source)
P
total
I
DDQ
∆I
DDQ
Power dissipation
2, 8, 9
Quiescent Supply Current
Quiescent Supply Current Delta
ACTS
V
IN
= V
DD
or V
SS
I
OL
= 12.0mA
I
OL
= 100µA
I
OH
= -12.0mA
I
OH
= -100µA
V
O
= V
DD
and V
SS
V
O
= V
DD
and V
SS
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
IN
= V
DD
or V
SS
V
OH
= V
DD
- 0.4V
C
L
= 50pF
V
DD
= 5.5V
For input under test
V
IN
= V
DD
- 2.1V
For all other inputs
V
IN
= V
DD
or V
SS
V
DD
= 5.5V
C
IN
C
OUT
Input capacitance
5
Output capacitance
5
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
15
15
pF
pF
2.1
10
1.6
mW/
MHz
µA
mA
-12
mA
.7V
DD
V
DD
- 0.25
-30
-300
12
30
300
.5V
DD
.7V
DD
-1
1
0.40
0.25
CONDITION
MIN
MAX
0.8
.3V
DD
UNIT
V
V
IH
V
I
IN
V
OL
µA
V
V
OH
V
µA
mA
mA
I
OZ
I
OS
I
OL
RadHard MSI Logic
238
UT54ACS541/UT54ACTS541
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
≤
5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose
≤
1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
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