HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM
WITH BUSY & INTERRUPT
Features
✵
◆
70121L
70125L
◆
High-speed access
– Commercial: 25ns (max.)
Low-power operation
– IDT70121/70125L
Active: 675mW (typ.)
Standby: 1mW (typ.)
MASTER IDT70121 easily expands data bus width to 18 bits or
more using SLAVE IDT70125 chip
◆
◆
◆
◆
◆
◆
◆
◆
Fully asychronous operation from either port
On-chip port arbitration logic (IDT70121 only)
BUSY
output flag on Master;
BUSY
input on Slave
INT
flag for port-to-port communication
Battery backup operation—2V data retention
TTL-compatible, signal 5V (±10%) power supply
Available in 52-pin PLCC
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
8L
I/O
Control
BUSY
L
A
10L
A
0L
(1,2)
I/O
0R
-I/O
8R
I/O
Control
BUSY
R
Address
Decoder
11
(1,2)
MEMORY
ARRAY
11
Address
Decoder
A
10R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
LOGIC
CE
R
OE
R
R/W
R
INT
L
(2)
INT
R
2654 drw 01
(2)
NOTES:
1. 70121 (MASTER):
BUSY
is non-tri-stated push-pull output.
70125 (SLAVE):
BUSY
is input.
2.
INT
is non-tri-stated push-pull output.
SEPTEMBER 2019
1
©2019 Integrated Device Technology, Inc.
DSC 2654/15
70121L/70125L
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and
Commercial Temperature Range
Description
The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port Static
RAMs. The IDT70121 is designed to be used as a stand-alone 9-bit Dual-
Port RAM or as a “MASTER” Dual-Port RAM together with the IDT70125
“SLAVE” Dual-Port in 18-bit-or-more word width systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 18-bit-or-wider memory
system applications results in full-speed, error-free operation without the
need for additional discrete logic.
Both devices provide two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power-down
feature, controlled by
CE,
permits the on-chip circuitry of each port to enter
a very low standby power mode.
The IDT70121/IDT70125 utilizes a 9-bit wide data path to allow for
Data/Control and parity bits at the user’s option. This feature is especially
useful in data communications applications where it is necessary to use a
parity bit for transmission/reception error checking.
Fabricated using CMOS high-performance technology, these
devices typically operate on only 675mW of power. Low-power (L)
versions offer battery backup data retention capability with each port
typically consuming 200µW from a 2V battery.
The IDT70121/IDT70125 devices are packaged in a 52-pin PLCC.
Pin Configurations
(1,2,3)
09/16/19
19
18
17
16
15
14
13
12
11
20
10
9
8
I/O
3L
I/O
2L
I/O
1L
I/O
0L
A
9L
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
8L
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
7
6
5
4
3
2
1
52
51
50
49
48
47
70121/125
PLG52
(4)
52-Pin PLCC
Top View
A
0L
OE
L
A
10L
INT
L
BUSY
L
R/W
L
CE
L
V
CC
CE
R
R/W
R
BUSY
R
INT
R
A
10R
I/O
7R
I/O
8R
A
9R
A
8R
A
7R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
OE
R
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately .75 in x .75 in x .17 in.
4. This package code is used to reference the package diagram.
2654 drw 02
2
6.42
70121L/70125L
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and
Commercial Temperature Range
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Unit
V
Recommended DC
Operating Conditions
Symbol
V
CC
GND
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
2654 tbl 03
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
o
C
C
V
IH
V
IL
o
mA
2654 tbl 01
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
cc
+ 10%.
Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
(1)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
2654 tbl 04
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Commercial
Industrial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
2654 tbl 02
NOTE:
1. This parameter is determined by device characterization but is not production
tested.
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 5.0V ± 10%)
70121S
70125S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
V
CC
= 5.5V,
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
___
70121L
70125L
Max.
10
10
0.4
___
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
2654 tbl 05
2.4
2.4
NOTE:
1. At Vcc < 2.0V leakages are undefined.
3
70121L/70125L
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and
Commercial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,4)
(V
CC
= 5V ± 10%)
70121X25
70125X25
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating Current
(Both Ports Active)
Test Condition
CE
= V
IL
, Outputs Disabled
f = f
MAX
(2)
Version
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
Typ.
135
135
___
___
70121X35
70125X35
Com'l
& Ind
Typ.
135
135
135
135
30
30
30
30
80
80
80
80
1.0
0.2
1.0
0.2
70
70
70
70
Max.
250
210
275
250
65
45
80
65
165
135
190
165
15
5
15
5
160
130
185
160
2654 tbl 06a
Max.
260
220
___
___
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL Level Inputs)
CE
"A"
=
CE
"B"
= V
IH
f = f
MAX
(2)
30
30
___
___
65
45
___
___
mA
I
SB2
Standby Current
(One Port - TTL Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(2)
80
80
___
___
175
145
___
___
mA
I
SB3
Full Standby Current (Both Ports
- CMOS Level Inputs)
CE
"A"
and
CE
"B"
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
VIN < 0.2V, f = 0
(3)
1.0
0.2
___
___
15
5
___
___
mA
I
SB4
Full Standby Current
(One Port - CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(2)
70
70
___
___
170
140
___
___
mA
70121X55
70125X55
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating Current
(Both Ports Active)
Test Condition
CE
= V
IL
, Outputs Disabled
f = f
MAX
(2)
Version
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
Typ.
135
135
___
___
Max.
240
200
___
___
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL Level Inputs)
CE
"A"
=
CE
"B"
= V
IH
f = f
MAX
(2)
30
30
___
___
65
45
___
___
mA
I
SB2
Standby Current
(One Port - TTL Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(2)
80
80
___
___
155
125
___
___
mA
I
SB3
Full Standby Current
(Both Ports - CMOS Level
Inputs)
CE
"A"
and
CE
"B"
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(3)
1.0
0.2
___
___
15
5
___
___
mA
I
SB4
Full Standby Current
(One Port - CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(2)
70
70
___
___
150
120
___
___
mA
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC
, and using “AC TEST CONDITIONS” of
input levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc=5V, T
A
=+25°C for Typ, and is not production tested.
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
2654 tbl 06b
4
6.42
70121L/70125L
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and
Commercial Temperature Range
Data Retention Characteristics
(L Version Only)
Symbol
V
DR
I
CCDR
t
CDR
(3)
t
R
(3)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
V
CC
= 2V,
CE
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2
IND.
COM'L.
Test Condition
Min.
2.0
___
___
Typ.
(1)
___
Max.
___
Unit
V
µA
100
100
___
4000
1500
___
t
RC
(2)
V
2654 tbl 07
NOTES:
1. V
CC
= 2V, T
A
= +25°C, and are not production tested.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed but is not production tested.
Data Retention Waveform
DATA RETENTION MODE
Vcc
4.5V
t
CDR
CE
V
IH
V
DR
V
DR
≥
2V
4.5V
t
R
V
IH
2654 drw 03
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
Figures 1 and 2
2654 tbl 08
5V
1250Ω
DATA
OUT
BUSY
INT
DATA
OUT
775Ω
30pF
775Ω
5V
1250Ω
5pF*
2654 drw 04
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(For t
LZ
, t
HZ
, t
WZ
, t
OW
)
*Including scope and jig.
5
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