电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

SY100E156

产品描述3-BIT 4:1 MUX-LATCH
文件大小63KB,共4页
制造商Microchip(微芯科技)
官网地址https://www.microchip.com
下载文档 选型对比 全文预览

SY100E156概述

3-BIT 4:1 MUX-LATCH

文档预览

下载PDF文档
3-BIT 4:1
MUX-LATCH
SY10E156
SY100E156
FINAL
FEATURES
s
s
s
s
s
s
900ps max. D to output
Extended 100E V
EE
range of –4.2V to –5.5V
800ps max. LEN to output
Differential outputs
Asynchronous Master Reset
Dual latch enables
DESCRIPTION
The SY10/100E156 offer three 4:1 multiplexers followed
by latches with differential outputs, designed for use in
new, high-performance ECL systems. The two external
latch enable signals (LEN
1
and LEN
2
) are gated through a
logical OR operation before use as control for the three
latches. When both LEN
1
and LEN
2
are at a logic LOW, the
latches are transparent, thus presenting the data from the
multiplexers at the output pins. If either LEN
1
or LEN
2
(or
both) are at a logic HIGH, the outputs are latched.
The multiplexer operation is controlled by the Select
(SEL
0
, SEL
1
) signals which select one of the four bits of
input data at each mux to be passed through.
The MR (Master Reset) signal operates asynchronously
to take all outputs to a logic LOW.
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E156
s
Available in 28-pin PLCC package
BLOCK DIAGRAM
PIN CONFIGURATION
D
2a
V
CCO
D
1b
D
1a
D
2d
D
2c
D
0a
D
0b
D
0c
D
0d
4:1
MUX
D
E
N R
Q
0
Q
0
SEL
0
SEL
1
MR
26
27
28
1
2
3
4
25 24 23 22 21 20 19
18
17
D
2b
Q
2
Q
2
V
CC
Q
1
Q
1
V
CCO
Q
0
D
1a
D
1b
D
1c
D
1d
D
4:1
MUX
E
N R
Q
1
Q
1
V
EE
LEN
1
LEN
2
D
1c
PLCC
TOP VIEW
J28-1
16
15
14
13
12
5
6
7
8
9
10 11
D
2a
D
2b
D
2c
D
2d
SEL
0
SEL
1
LEN
1
LEN
2
MR
D
4:1
MUX
E
N R
Q
2
Q
2
PIN NAMES
Pin
D
0x
–D
2x
SEL
0
, SEL
1
LEN
1
, LEN
2
MR
Q
0
–Q
2
Q
0
–Q
2
V
CCO
Function
Input Data
Select Inputs
Latch Enables
Master Reset
True Outputs
Inverted Outputs
V
CC
to Output
Rev.: C
Amendment: /1
1
V
CCO
Q
0
Issue Date: February, 1998
D
1d
D
0a
D
0b
D
0c
D
0d

SY100E156相似产品对比

SY100E156 SY100E156JCTR SY100E156JC SY10E156JC SY10E156JCTR SY10E156
描述 3-BIT 4:1 MUX-LATCH 3-BIT 4:1 MUX-LATCH 3-BIT 4:1 MUX-LATCH 3-BIT 4:1 MUX-LATCH 3-BIT 4:1 MUX-LATCH 3-BIT 4:1 MUX-LATCH

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 572  1680  198  2179  22  9  30  56  18  11 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved