Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power supply: 2.5V ± 0.20V
Standard 200 pin SO-DIMM package
• Package height options:
BD4: 31.75mm (1.25")
NOTE: Consult factory for availability of:
• Lead-Free or RoHS Products
• Vendor source control options
• Industrial temperature option
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
DESCRIPTION
The WV3EG6434S is a 32Mx64 Double Data Rate
SDRAM memory module based on 256Mb DDR
SDRAM component. The module consists of eight
32Mx8 DDR SDRAMs in BGA package mounted on a
200 Pin FR4 substrate.
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lenths allow the
same device to be useful for a variety of high bandwidth,
high performance memory system applications.
OPERATING FREQUENCIES
DDR333 @CL=2.5
Clock Speed
CL-t
RCD
-t
RP
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Symbol
V
REF
V
REF
V
SS
V
SS
DQ0
DQ4
DQ1
DQ5
V
CC
V
CC
DQS0
DM0
DQ2
DQ6
V
SS
V
SS
DQ3
DQ7
DQ8
DQ12
V
CC
V
CC
DQ9
DQ13
DQS1
DM1
V
SS
V
SS
DQ10
DQ14
DQ11
DQ15
V
CC
V
CC
CK0
V
CC
CK0#
V
SS
V
SS
V
SS
DQ16
DQ20
DQ17
DQ21
V
CC
V
CC
DQS2
DM2
DQ18
DQ22
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
V
SS
V
SS
DQ19
DQ23
DQ24
DQ28
V
CC
V
CC
DQ25
DQ29
DQS3
DM3
V
SS
V
SS
DQ26
DQ30
DQ27
DQ31
V
CC
V
CC
NC
NC
NC
NC
V
SS
V
SS
*DQS8
*DM8
NC
NC
V
CC
V
CC
NC
NC
NC
NC
V
SS
V
SS
*CK2
V
SS
*CK2#
V
CC
V
CC
V
CC
*CKE1
CKE0
NC
NC
A12
A11
Pin
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Symbol
A9
A8
V
SS
V
SS
A7
A6
A5
A4
A3
A2
A1
A0
V
CC
V
CC
A10/AP
BA1
BA0
RAS#
WE#
CAS#
CS0
*CS1#
NC
NC
V
SS
V
SS
DQ32
DQ36
DQ33
DQ37
V
CC
V
CC
DQS4
DM4
DQ34
DQ38
V
SS
V
SS
DQ35
DQ39
DQ40
DQ44
V
CC
V
CC
DQ41
DQ45
DQS5
DM5
V
SS
V
SS
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Symbol
DQ42
DQ46
DQ43
DQ47
V
CC
V
CC
V
CC
*CK1#
V
SS
*CK1
V
SS
V
SS
DQ48
DQ52
DQ49
DQ53
V
CC
V
CC
DQS6
DM6
DQ50
DQ54
V
SS
V
SS
DQ51
DQ55
DQ56
DQ60
V
CC
V
CC
DQ57
DQ61
DQS7
DM7
V
SS
V
SS
DQ58
DQ62
DQ59
DQ63
V
CC
V
CC
SDA
SA0
SCL
SA1
V
CCSPD
SA2
NC
NC
WV3EG6434S-BD4
ADVANCED
PIN NAMES
A0 – A12
BA0-BA1
DQ0-DQ63
DQS0-DQS7
CK0
CK0#
CKE0
CS0#
RAS#
CAS#
WE#
DM0-DM7
V
CC
V
CCQ
V
SS
V
REF
V
CCSPD
SDA
SCL
SA0-SA2
V
CCID
NC
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Data Strobe Input/Output
Clock input
Clock input
Clock Enable Input
Chip select Input
Row Address Strobe
Column Address Strobe
Write Enable
Data-In Mask
Power Supply
Power Supply for DQS
Ground
Power Supply for Reference
Serial EEPROM Power Supply
Serial data I/O
Serial clock
Address in EEPROM
V
CC
Identification Flag
No Connect
* These pins are not used in this module.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
S0# CKE0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S0#
WV3EG6434S-BD4
ADVANCED
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S0#
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S1#
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S1#
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S0#
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S0#
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S1#
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S1#
BA0 - BA1
A0 - A12
RAS#
CAS#
WE#
BA0-BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: SDRAMs
CAS#: SDRAMs
WE#: SDRAMs
Serial PD
SCL
WP
A0
SA0
A1
SA1
A2
SA2
SDA
V
CCSPD
V
CC
/V
CCQ
SPD
DDR SDRAM
CK0
CK0#
PLL
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
V
REF
V
SS
DDR SDRAM
DDR SDRAM
NOTE: All resistor values are 22 ohms unless otherwise specified.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Current
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
WV3EG6434S-BD4
ADVANCED
Symbol
V
IN
, V
OUT
V
CC
, V
CCQ
T
STG
P
D
I
OS
Value
-0.5 to 3.6
-1.0 to 3.6
-55 to +150
8
50
Units
V
V
°C
W
mA
DC OPERATING CONDITIONS
T
A
= 0°C to 70°C
Parameter
Supply voltage(for device with a nominal V
CC
of 2.5V)
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage (system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CK and CK# inputs
Input Differential Voltage, CK and CK# inputs
Input crossing point voltage, CK and CK# inputs
Input leakage current
Output leakage current
Output High Current(Normal strengh driver); V
OUT
= V
TT
+ 0.84V
Output High Current(Normal strengh driver); V
OUT
= V
TT
- 0.84V
Output High Current(Half strengh driver); V
OUT
= V
TT
+ 0.45V
Output High Current(Half strengh driver); V
OUT
= V
TT
- 0.45V
Symbol
V
CC
V
CCQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
(DC)
V
ID
(DC)
V
IX
(DC)
I
I
I
OZ
I
OH
I
OL
I
OH
I
OL
Min
2.3
2.3
V
CCQ
/2-50mV
V
REF
-0.04
V
REF
+0.15
-0.3
-0.3
0.3
1.15
-2
-5
-16.8
16.8
-9
9
Max
2.7
2.7
V
CCQ
/2+50mV
V
REF
+0.04
V
CCQ
+0.3
V
REF
-0.15
V
CCQ
+0.3
V
CCQ
+0.6
1.35
2
5
Unit
V
V
V
V
V
V
V
V
V
uA
uA
mA
mA
mA
mA
Note
1
2
4
4
3
5
Notes:
1. Includes ± 25mV margin for DC offset on V
REF
, and a combined total of ± 50mV margin for all AC noise and DC offset on V
REF
, bandwidth limited to 20MHz. The DRAM must
accommodate DRAM current spikes on V
REF
and internal DRAM noise coupled TO V
REF
, both of which may result in V
REF
noise. V
REF
should be de-coupled with an inductance of ≤ 3nH.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
, and must track variations in the DC level of V
REF
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a
V
REF
envelop that has been bandwidth limited to 200MHZ.
5. The value of V
IX
is expected to equal 0.5*V
CCQ
of the transmitting device and must track variations in the dc level of the same.
CAPACITANCE
T
A
= 25°C, f = 1MHz, V
CC
= 2.5V, V
REF
=2.5V
±
200mV
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS#, CAS#, WE#)
Input Capacitance (CKE0)
Input Capacitance (CK0,CK0#)
Input Capacitance (CS0#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
April 2005
Rev. 0
4
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN6
C
IN7
C
OUT
Max
21
21
21
3
12
10
21
10
Unit
pF
pF
pF
pF
pF
pF
pF
pF
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3EG6434S-BD4
ADVANCED
I
DD
SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C ≤ T
A
≤ 70°C, V
CCQ
= 2.5V ±0.2V, V
CC
= 2.5V ±0.2V
DDR333@
CL=2.5
Parameter
Operating Current
Symbol Conditions
I
DD0
One device bank; Active - Precharge; t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN);
DQ,DM and DQS inputs changing once per clock cycle; Address
and control inputs changing once every two cycles.
One device bank; Active-Read-Precharge; Burst = 2; t
RC
=t
RC
(MIN
);t
CK
=t
CK
(MIN); Iout = 0mA; Address and control inputs changing
once per clock cycle.
All device banks idle; Power- down mode; t
CK
=t
CK
(MIN);
CKE=(low)
CS# = High; All device banks idle; t
CK
=t
CK
(MIN); CKE = high;
Address and other control inputs changing once per clock cycle.
Vin = Vref for DQ, DQS and DM.
CS# > = V
IH
(min); All banks idle; CKE > = V
IH
(min); t
CK
= 100Mhz
for DDR200, 133Mhz for DDR266A & DDR266B; Address and
other control inputs stable with keeping >= V
IH
(min) or =
< V
IL
(max); V
IN
= V
REF
for DQ, DQS and DM
One device bank active; Power-down mode; t
CK
(MIN); CKE=(low)
CS# = High; CKE = High; One device bank; Active-Precharge;
t
RC
=t
RAS
(MAX); t
CK
=t
CK
(MIN); DQ, DM and DQS inputs changing
twice per clock cycle; Address and other control inputs changing
once per clock cycle.
Burst = 2; Reads; Continous burst; One device bank
active;Address and control inputs changing once per clock cycle;
t
CK
=t
CK
(MIN); Iout = 0mA.
Burst = 2; Writes; Continous burst; One device bank active;
Address and control inputs changing once per clock cycle;
t
CK
=t
CK
(MIN); DQ,DM and DQS inputs changing twice per clock
cycle.
t
RC
=t
RC
(MIN)
CKE
≤
0.2V
Four bank interleaving Reads (BL=4) with auto precharge with
t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); Address and control inputs change
only during Active Read or Write commands.
Max
720
DDR266@
CL=2
Max
640
DDR266@
CL=2.5
Max
640
Units
mA
920
840
840
mA
Operating Current
Precharge Power-Down
Standby Current
Idle Standby Current
I
DD1
I
DD2P
24
240
24
200
24
200
mA
mA
I
DD2F
200
185
185
mA
Precharge Quiet
Standby Current
Active Power-Down
Standby Current
I
DD2Q
I
DD3P
280
440
240
360
240
360
mA
mA
Active Standby Current
I
DD3N
1280
1120
1120
mA
Operating Current
I
DD4R
1280
1080
1080
mA
Operating Current
I
DD4W
Auto Refresh Current
Self Refresh Current
Operating Current
I
DD5
I
DD6
I
DD7A
1360
24
2240
1280
24
2080
1280
24
2080
mA
mA
mA
Note: I
DD
speicification is based on Samsung components. Other DRAM manufacturers specification may be different.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
