VSC8147
Datasheet
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STS-48/STM-16 (FEC) 4:1 SONET/SDH Transceiver with Integrated CRU/CMU
Features
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•
•
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•
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•
STS-48/STM-16, FEC
Wide-ranging PLLs
Exceeds Telcordia SONET jitter specifications
High-speed data I/O and clock outputs
High-speed clock output power-down option
Low-speed 4-bit LVDS I/O
LOS and LOL detect with automatic Lock to
Reference
•
•
•
•
•
•
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On-board FIFO
Equipment and Facility Loopback modes
Rx/Tx internal Loop Timing mode
Single 2.5V power supply
800mW typical power dissipation
0.18µm CMOS technology
100-pin LQFP, 14mm x 14mm x 1.4mm package
General Description
The VSC8147 is an electrical transceiver with an integrated clock recovery unit (CRU) and clock multiplier unit
(CMU) for use in SONET/SDH systems operating at STS-48/STM-16 and Forward Error Correction (FEC) data
rates.
The integrated CRU phase-locked loop (PLL) recovers the high-speed clock from the input data. The integrated CMU
PLL multiplies a low-speed reference clock to provide the high-speed serial line clock for internal logic and output
retiming. The parallel 4-bit LVDS interface incorporates an onboard FIFO, eliminating loop timing issues. The
VSC8147 supports Facility and Equipment Loopback modes.
The Loss of Lock (LOL) status signal indicates loss of lock of the PLL and the Loss of Signal (LOS) status signal
indicates the occurrence of an all-0s or an all-1s pattern. During a LOS condition, an all-0s data pattern is generated,
along with a SONET-quality clock (for SONET rates only).
If an LOS condition occurs, the PLL automatically switches to the reference clock and then switches back to the high-
speed input when the LOS signal is deasserted.
The VSC8147 operates using a single 2.5V supply with 800mW typical power dissipation and is available in a
thermally enhanced, 100-pin plastic LQFP package.
G52397 Revision 4.1
September 20, 2005
©
VITESSE SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • E-mail: prodinfo@vitesse.com
Internet: www.vitesse.com
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VSC8147
Datasheet
RSDIP
RSDIN
LOS
Detect
Divide
by 4
0
1
4
C
L
K
RCLK4P
RCLK4N
RD
Reg
RDO0P
RDO0N
RDO3P
RDO3N
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CRULOS
CRULOL
RFILT
Clock Recovery
Unit
1:4
Serial-to-Parallel
Demux
0
4
1
D
A
T
A
4
LPBKEQU
155MHz
Write
C
L
K
1
0
4
TD
Reg
4
TCLK4IP
TCLK4IN
TDI0P
TDI0N
TDI3P
TDI3N
LPBKFAC
RESET
SPILL
TSDOP
TSDON
TSCLKOP
TSCLKON
CLKPD
4:1
Parallel-to-Serial
Mux
4x8
FIFO
4
D
A
T
A
1
0
Divide
by 4
Read
TCLK4OP
TCLK4ON
1
REFCLKP
REFCLKN
LPTM
MFILT
0
R
C
L
K
Clock Multiplier
Unit
Power
CMULOL
VDDI (2.5V)
VDDNCAP
Figure 1. VSC8147 Block Diagram
VSC8147
VSC7969
TIA/PA
Optics
VSC7939
LD
CMU/Mux
4
4
CRU/Demux
VSC9115
Interleaver
or
VSC9271
FEC/PM
or
VSC9186
Pointer
Processor
Figure 2. System Solution
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G52397 Revision 4.1
September 20, 2005
VSC8147
Datasheet
Functional Description
Receiver Operation
The on-chip receiver is composed of a CRU, a 1:4 demultiplexer, and I/O buffers to support SONET/SDH STS-48
and STS-48 FEC data rates.
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Clock Recovery Unit (CRU)
The CRU accepts high-speed NRZ data (RSDI) and recovers the clock for demultiplexer timing and downstream
devices. The on-chip PLL consists of a phase detector, loop filter, and voltage-controlled oscillator (VCO). When
there is a phase error between the incoming data and the on-chip VCO, the loop filter raises or lowers the control
voltage of the VCO to nullify the phase difference. One external filter capacitor (3.3µF, 1206 size, ceramic Y5V, 6-
10WVDC) connected from the loop filter pin (RFILT) to ground is required for normal operation of the CRU. This
circuit complies with SONET jitter tolerance requirements.
One reference clock, REFCLK, is provided as input to the VSC8147. The frequency of the REFCLK input to the
CRU is 155MHz to 166MHz. See
Table 1.
Table 1. Recommended CRU/CMU REFCLK Frequencies
STS-48
155.52MHz
STS-48 FEC
166.67MHz
CRU Loss of Signal
A CRU LOS detector monitors the incoming high-speed data and detects within 2.3µs to 100µs if the signal is stuck in
a constant state (all 1s or 0s). Upon detection, the CRU generates an LVTTL-level LOS indicator (CRULOS LOW
indicates loss of signal) to reflect this condition. See
Table 2.
The CRU automatically locks to the selected REFCLK
input and presents all 0s on the low-speed parallel output data bus (RDO[0:15]). During this condition, the low-speed
receive clock output (RCLK16) provides a continuous clock phase and remains frequency-locked within ±20ppm to
the selected REFCLK input.
The CRU continuously monitors the high-speed data input to determine if data is present. When data is restored at the
high-speed input, the CRU automatically switches from locking on the reference clock to locking back on incoming
data signal within 125µs to 250µs. See
Table 2.
The performance of the CRU Loss of Signal detector is highly dependent on the operating environment. When used
with an optical transceiver module, it is recommended to use the LOS alarm from the module, rather than the CRU
LOS detector.
Table 2. CRU LOS Parameters
Symbol
t
LOS_SET
t
LOS_CLEAR
Parameter
LOS set Time
LOS clear Time
Min
2.3
125
Typ
Max
100
250
Unit
µs
µs
Condition
From data interruption.
From data restoration.
CRU Loss of Lock
To support system administrative and maintenance applications, a CRU LOL (CRULOL) detector indicates when the
internal PLL loses lock to the incoming data signal. This LOL condition occurs if the incoming high-speed data
signal is lost, severely degraded, or falls outside the lock range of the PLL. The low-speed receive clock output
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VSC8147
Datasheet
(RCLK4) provides a continuous clock that is frequency-locked within ±400ppm to the REFCLK input during this
condition. The CRULOL output pin is LVTTL level (CRULOL LOW indicates loss of lock).
Table 3
lists the LOL
specifications.
Table 3. CRU LOL Parameters
Symbol
t
LOL_SET
t
LOL_CLEAR
Parameter
LOL set time
LOL clear time
Min
Typ
1
500
Max
Unit
ms
µs
Condition
From data interruption.
From data restoration.
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To further clarify the automatic lock to reference clock operation,
Table 4
summarizes the various states in which the
VSC8147 will operate during this condition.
Table 4. Automatic Lock to Reference Clock States
State
0
1
2
3
Description
Device powered off.
Normal operation—device is powered on
and lockable input data is present.
Clean LOS operation—device is powered
on and static 1 or 0 input data is present.
LOL or Dirty LOS operation—device is
powered on, and unlockable input data,
other than static 1 or 0, is present.
CRULOS
N/A
1
0
1
CRULOL
N/A
1
1
0
N/A
Phase-locked to input
data.
Phase-locked to
REFCLK.
Frequency-locked to
REFCLK within
±
400ppm.
RCLK4
N/A
Retimed RSDI with 0%
BER.
Static logic 0.
Static logic 0, but may
toggle depending on the
quality of the input
signal.
RDO[0:3]
A ‘clean’ LOS operation occurs when the incoming optical receiver stops receiving the incoming signal (such as due
to a fiber cut) and the optical receiver electronics go to either a static logic 1 or logic 0 state.
A ‘dirty’ LOS operation can occur due to the same condition as a clean LOS occurrence except that the optical
receiver does not go to a static logic 1 or 0, but instead oscillates and generates random, unlockable data to the
downstream device. This occurrence will be seen as an LOL condition.
Demultiplexer, Serial-to-Parallel Conversion
A demultiplexer in the VSC8147 converts high-speed serial data (RSDI) into four low-speed parallel outputs
(RDO[0:3]). A divide-by-4 clock (RCLK4) provides timing of upstream devices and outputs a SONET-compliant
clock signal, provided REFCLK receives a SONET-compliant clock signal.
Transmitter Operation
The on-chip transmitter is comprised of a CMU, a 4:1 multiplexer, a First-In-First-Out (FIFO) Elastic Store buffer,
and all the I/O buffers to support SONET/SDH STS-48 and STS-48 FEC data rates.
Clock Multiplier Unit (CMU)
The CMU accepts the low-speed clock input and generates a high-speed clock output for serial retiming. The on-chip
PLL consists of a phase detector, a loop filter, and a VCO. Although the clock input to the CMU tolerates as much as
±100ppm, it must have a frequency accuracy of ±20ppm or better to ensure SONET/SDH compliance on the output.
This circuit complies with SONET jitter generation requirements. An external filter capacitor (3.3µF, 1206 size,
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G52397 Revision 4.1
September 20, 2005
VSC8147
Datasheet
ceramic Y5V, 6-10WVDC), connected from the loop filter pin (MFILT) to ground, is required for operation of the
CMU.
One reference clock (REFCLK) is provided as input to the VSC8147. The frequency of the REFCLK input to the
CRU is 155MHz to 166MHz. See
Table 1,
page 3.
The CMU can use either the REFCLK input or the 155MHz internal clock output from the CRU as the low-speed
clock input. SONET jitter compliance is not guaranteed if CLK155 is used.
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CMU Loss of Lock
A CMU LOL (CMULOL) signal indicates when the CMU loses lock to the incoming clock. The CMULOL signal is
an active LOW signal.
Table 5
lists the LOL specifications.
Table 5. CMU LOL Parameters
Symbol
t
LOL_SET
t
LOL_CLEAR
Parameter
LOL set time
LOL clear time
Min
Typ
1
500
Max
Unit
ms
µs
Condition
From data interruption.
From data restoration.
Multiplexer, Parallel-to-Serial Conversion
The VSC8147 uses a multiplexer to convert 16 low-speed parallel inputs (TDI[0:13]) into high-speed serial clock
(TSCLKO) and data (TSDO) outputs. Most optical modules and laser drivers do not require a clock signal. If the
TSCLKO output is not required, it can be powered down by an external LVTTL control pin to reduce power
consumption (CLKPD HIGH disables TSCLKO). If no connection is made to CLKPD, the default setting is
TSCLKO on.
Figure 3
shows that when interfacing on the low-speed transmitter side, the upstream device should use the
TCLK16O as the timing source for its final output latch.
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G52397 Revision 4.1
September 20, 2005
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