®
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7186-01
Features
• Four Complete Transceiver Functions in One IC
• Full Gigabit Ethernet (IEEE 802.3z) Compliance
• Pin-Compatible With Agilent’s HDMP-1686A
• 5V Tolerant TTL Inputs
• Utilizes Reference Clock to Latch Tx Data
• Receiver Squelch Circuit
• Common Local Loopback Control
Quad Transceiver
for Gigabit Ethernet and Fibre Channel
• Single Comma Detect Enable
• Cable Equalization in Receivers
• Automatic Lock-to-Reference
• TAG Access Port
• 2kV ESD Protection on All Pins
• 3.3V Power Supply, 2.67 W Max Dissipation
• 208-Pin, 23mm BGA Packaging
General Description
The VSC7186-01 is a quad Gigabit Ethernet transceiver IC. Each of the four transmitters has a 10-bit wide
bus, running at 125MHz, which accepts 8B/10B encoded transmit characters and serializes the data onto high-
speed differential outputs at rates between 1.05Gb/s and 1.36Gb/s. The transmit data must be synchronous to
the reference clock. Each receiver samples serial receive data, recovers the clock and data, deserializes it into
10-bit receive characters, outputs a recovered clock and detects “Comma” characters. The VSC7186-01 con-
tains on-chip (Phase-Lock Loop) PLL circuitry for synthesis of the baud-rate transmit clock and extraction of
the clocks from the received serial streams. The VSC7186-01 also includes a receiver squelch circuit to control
the parallel data bus in the absence of serial input.
VSC7186-01 Block Diagram (1 of 4 Channels)
RXi(0:9)
10
QD
Serial to
Q Parallel D
QD
0
Clock
Recovery
÷10
Unit
1
SI+
SI-
RCM
RCi1
RCi0
SYNi
SYNC
LOOP
Comma
Detect
SEL
÷10/
÷20
TXi[0:9)
10
DQ
Parallel
to Serial
DQ
SO+
SO-
RFC1
CAP0
CAP1
Clock
Multiply
Unit
x10
G52348-0, Rev 2.2
10/10/00
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 1
®
VITESSE
SEMICONDUCTOR CORPORATION
Quad Transceiver
for Gigabit Ethernet and Fibre Channel
Advance Product Information
VSC7186-01
Functional Description
Notation
In this document, each of the four channels are identified as Channel 0, 1, 2 or 3. When discussing a signal
on any specific channel, the signal will have the channel number embedded in the name, for example,
“T3[0:9].” When referring to the common behavior of a signal which is used on each of the four channels, the
notation “i” is used. Differential signals, such as SOi+ and SOi-, may be referred to as a single signal (e. g., SOi)
by dropping reference to the “+” and “-.”
Clock Synthesizer
The VSC7186-01 Clock Multiplier Unit (CMU) multiplies the reference frequency provided on the RFC1
input by 10 to achieve a baud rate clock between 1.05GHz and 1.36GHz. The RFC1 input is TTL. The on-chip
PLL uses a single external 0.1µF capacitor, connected between CAP0 and CAP1, to control the Loop Filter.
This capacitor should be a multilayer ceramic dielectric, or better, with at least a 5V working voltage rating and
a good temperature coefficient (NPO is preferred but X7R may be acceptable). These capacitors are used to
minimize the impact of common-mode noise on the CMU, especially power supply noise. Higher value capaci-
tors provide better robustness in systems. NPO is preferred because if an X7R capacitor is used, the power sup-
ply noise sensitivity will vary with temperature.
For best noise immunity, the designer may use a three capacitor circuit with one differential capacitor
between CAP0 and CAP1, C1, a capacitor from CAP0 to ground, C2, and a capacitor from CAP1 to ground,
C3. Larger values are better but 0.1µF is adequate. However, if a three capacitor circuit cannot be used, a sin-
gle differential capacitor, C1, is adequate. These components should be isolated from noisy traces.
Figure 1: Loop Filter Capacitors (Best Circuit)
CAP0
C2
C1
C3
VSC7186-01
CAP1
C1=C2=C3= >0.1µF
MultiLayer Ceramic
Surface Mount
NPO (preferred) or X7R
5V Working Voltage Rating
Serializer
The VSC7186-01 accepts TTL input data as four parallel 10-bit characters on the Ti[0:9] buses which are
latched into the input registers on the rising edge of RFC1. The 10-bit parallel transmission character will be
serialized and transmitted on the SOi+/- PECL differential outputs at the baud rate with bit Ti0 (bit A) transmit-
ted first. User data should be encoded using 8B/10B or an equivalent code. The mapping to 10B encoded bit
nomenclature and transmission order is shown in Table 1, along with the recognized comma pattern.
Table 1: Transmission Order and Mapping of a 10b Character
Data Bit
10B Bit Position
Comma Character
T9
j
x
T8
h
x
T7
g
x
T6
f
1
T5
i
1
T4
e
1
T3
d
1
T2
c
1
T1
b
0
T0
a
0
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52348-0, Rev 2.2
10/10/00
®
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7186-01
Quad Transceiver
for Gigabit Ethernet and Fibre Channel
Clock Recovery
The VSC7186-01 accepts differential high-speed serial input from the selected source (either the PECL
SIi+/- pins or the internal SOi+/- data), extracts the clock and retimes the data. Equalizers are included in the
receiver to open the data eye and compensate for Intersymbol Interference (ISI) which may be present in the
incoming data. The serial bit stream should be encoded so as to provide DC balance and limited run length by
an 8B/10B encoding scheme. The digital Clock Recovery Unit (CRU) is completely monolithic and requires no
external components. For proper operation, the baud rate of the data stream to be recovered should be within
+200ppm of ten times the REF frequency. For example, Gigabit Ethernet systems use 125MHz oscillators with
a +/-100ppm accuracy resulting in +/-200ppm between VSC7186-01 pairs.
Deserializer
The recovered serial bit stream is converted into a 10-bit parallel output character. The VSC7186-01 pro-
vides complementary TTL recovered clocks, RCi0 and RCi1, at 1/20th of the serial baud rate if RCM=LOW, or
a single clock at 1/10th the serial baud rate (on RCi1 only) if RCM=HIGH. The clocks are generated by divid-
ing down the high-speed recovered clock which is phase-locked to the serial data. The serial data is retimed,
deserialized and output on Ri[0:9].
If serial input data is not present, or does not meet the required baud rate, the VSC7186-01 will continue to
produce a recovered clock so that downstream logic may continue to function. The RCi0/RCi1 output frequency
under these circumstances will differ from its expected frequency by no more than +1%.
Word Alignment
The VSC7186-01 provides 7-bit comma character recognition and data word alignment. Word synchroniza-
tion is enabled on all channels by asserting SYNC HIGH. When synchronization is enabled, the receiver exam-
ines the recovered serial data for the presence of the “Comma” pattern. This pattern is “0011111XXX”, where
the leading zero corresponds to the first bit received. The comma sequence is not contained in any normal 8B/
10B coded data character or pair of adjacent characters. It occurs only within special characters, known as
K28.1, K28.5 and K28.7, which are defined for synchronization purposes. Improper comma alignment is
defined as any of the following conditions:
1) The comma is not aligned within the 10-bit transmission character such that Ri[0...6) = “0011111.”
2) The comma straddles the boundary between two 10-bit transmission characters.
3) The comma is properly aligned but occurs in the received character presented during the rising edge of
RCi0 rather than RCi1.
When an improperly aligned comma is encountered, the recovered clock is stretched, never slivered, so that
the comma character and recovered clocks are aligned properly to Ri[0:9]. This results in proper character and
word alignment. When the parallel data alignment changes in response to a improperly aligned comma pattern,
data which would have been presented on the parallel output port prior to the comma character, and possibly the
comma character itself, may be lost. Possible loss of the comma character is data dependent, according to the
relative change in alignment. Data subsequent to the comma character will always be output correctly and prop-
erly aligned.
G52348-0, Rev 2.2
10/10/00
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 3
®
VITESSE
SEMICONDUCTOR CORPORATION
Quad Transceiver
for Gigabit Ethernet and Fibre Channel
Advance Product Information
VSC7186-01
On encountering a comma character, SYNi is driven HIGH. The SYNi pulse is presented simultaneously
with the comma character and has a duration equal to the data. The SYNi signal is timed such that it can be cap-
tured by the adjoining protocol logic on the rising edge of RCi1. Functional waveforms for synchronization are
given in Figure 2. The first K28.5 shows the case where the comma is detected, but it is misaligned so a change
in the output data alignment is required. Note that up to three characters prior to the comma character may be
corrupted by the realignment process. The second K28.5 shows the case when a comma is detected and no
phase adjustment is necessary. It illustrates the position of the SYNi pulse in relation to the comma character on
Ri[0:9].
Figure 2: Misaligned and Aligned K28.5 Characters
RCi0
(RCM LOW)
RCi1
RCi0
([RCM HIGH)
RCi1
SYNi
RXi[0:9]
Data
Corrupt
Corrupt
Corrupt
K28.5
Data1
Data2
Data3
K28.5
Misaligned Comma: Stretched
Aligned Comma
Loopback Operation
Loopback operation is controlled by the LOOP line. When this line is HIGH, the outgoing high-speed
serial data on each of the four channels is internally looped back into that channel’s high-speed serial receiver
section. This provides for in-circuit testing capability independent of the transmission medium.
JTAG Access Port
A JTAG access port is provided to assist in board-level testing. Through this port most pins can be accessed
or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this device is
available in “VSC7186-01 JTAG Access Port Functionality.” Circuits designed exclusively for the HDMP-
1686A will automatically disable the JTAG port. Refer to Table 5 for proper connections for either HDMP-
1686A emulation or for JTAG functionality (in parentheses).
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52348-0, Rev 2.2
10/10/00
®
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7186-01
AC Characteristics
Quad Transceiver
for Gigabit Ethernet and Fibre Channel
Figure 3: Transmit Timing Waveforms
RFC1
T
1
T
2
TXi[0:9]
10-Bit Data
Data Valid
Data Valid
Data Valid
+/-SOi
T
LAT
S0
S1
S2
RFC1
Table 2: Transmitter AC Characteristics
Parameter
T
1
T
2
T
SDR
,T
SDF
T
LAT
Description
Ti[0:9] setup time to the rising
edge of RFC1
Ti[0:9] hold time after the
rising edge of RFC1
Ti+/Ti- rise and fall time
Latency from rising edge of
RFC1 to Ti0 appearing on SO
bit 0i
Min
1.5
Typ
—
Max
—
Units
ns
Conditions
Measured between the valid data
level of Ti[0:9] to the 1.4V point of
RFC1
1.0
—
7bc +
0.66ns
—
—
—
—
300
7bc +
1.46ns
ns
ps
20% to 80%, 75Ω load to V
DD
/2,
tested on a sample basis
bc = bit clocks
ns = nanoseconds
Transmitter Output Jitter
RJ
DJ
Random jitter (rms)
Serial data output deterministic
jitter (pk-pk)
—
—
5
35
8
80
ps
ps
Measured at SO+/-, 1 sigma
deviation of 50% crossing point
IEEE 802.3Z Clause 38.68, tested
on a sample basis
G52348-0, Rev 2.2
10/10/00
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 5
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