SPT
SIGNAL PROCESSING TECHNOLOGIES
SPT7760
8-BIT, 1 GSPS FLASH A/D CONVERTER
APPLICATIONS
•
•
•
•
Digital Oscilloscopes
Transient Capture
Radar, EW, ECM
Direct RF Down-Conversion
FEATURES
•
•
•
•
•
•
1:2 Demuxed ECL Compatible Outputs
Wide Input Bandwidth - 900 MHz
Low Input Capacitance - 15 pF (MQUAD)
Metastable Errors Reduced to 1 LSB
Monolithic for Low Cost
Gray Code Output
GENERAL DESCRIPTION
The SPT7760 is a full parallel (flash) analog-to-digital con-
verter capable of digitizing full scale (0 to -2 V) inputs into
eight-bit digital words at an update rate of 1 GSPS. The ECL-
compatible outputs are demultiplexed into two separate
output banks, each with differential data ready outputs to
ease the task of data capture. The SPT7760's wide input
bandwidth and low capacitance eliminate the need for exter-
nal track-and-hold amplifiers for most applications. A propri-
CLK CLK
etary decoding scheme reduces metastable errors to the
1 LSB level. The SPT7760 operates from a single -5.2 V
supply, with a nominal power dissipation of 5.5 W.
The SPT7760 is available in an 80L surface-mount MQUAD
package over the industrial temperature range. Contact the
factory for availability of die and /883 versions.
BLOCK DIAGRAM
Analog
V
RT Input
Preamp
Comparator
256
CLOCK
BUFFER
DEMUX
CLOCK
BUFFER
255
D8
(OVR)
D8B
D7B
•
•
D5B
•
•
D2B
152
256 TO 8 BIT DECODER
WITH METASTABLE ERROR CORRECTION
D7
(MSB)
D6
151
D5
1:2 DEMULTIPLEXER
128
D1B
D0B
D8A
D7A
•
•
•
D5A
•
•
•
D2A
D1A
D0A
V
RM
127
D4
64
D3
63
D2
2
D1
DRB (DATA READY)
DRB (DATA READY)
D8B (OVR)
D7B (MSB)
D6B
D5B
D4B
D3B
D2B
D1B
D0B (LSB)
DRA (DATA READY)
DRA (DATA READY)
D8A (OVR)
D7A (MSB)
D6A
D5A
D4A
D3A
D2A
D1A
D0A (LSB)
1
DO
(LSB)
V
RB
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
ECL OUTPUT BUFFERS AND LATCHES
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25
°
C
Supply Voltages
Negative Supply Voltage (V
EE
TO GND) ......... .-7.0 to +0.5 V
Ground Voltage Differential ............................. .-0.5 to +0.5 V
Input Voltage
Analog Input Voltage ........................................ +0.5 V to V
EE
Reference Input Voltage .................................. +0.5 V to V
EE
Digital Input Voltage ......................................... +0.5 V to V
EE
Reference Current V
RT
to V
RB
.................................... 35 mA
Output
Digital Output Current ........................................ 0 to -28 mA
Temperature
Operating Temperature, ambient ...................... .-25 to +85
°C
case ................................... +125
°C
junction ............................... +150
°C
Lead Temperature, (soldering 10 seconds). ............. +300
°C
Storage Temperature ...................................... -65 to +150
°C
Notes:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied condi-
tions in typical applications.
ELECTRICAL SPECIFICATIONS
T
J
= T
C
= T
A
= +25
°C
, V
EE
=-5.2 V, V
RB
=-2.00 V, V
RM
=-1.0 V, V
RT
=0.00 V, f
clk
=1 GHz, Duty Cycle=50%, unless otherwise specified.
PARAMETERS
Resolution
DC Accuracy (+25
°C)
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
Analog Input
Input Voltage Range
Input Bias Current
Input Resistance
Input Capacitance
Input Bandwidth
Small Signal
Large Signal
Offset Error V
RT
Offset Error V
RB
Input Slew Rate
Clock Synchronous
Input Currents
Reference Input
Ladder Resistance
Reference Bandwidth
Timing Characteristics
Maximum Sample Rate
Aperture Jitter
Acquisition Time
CLK to Data Ready Delay
Clock to Data Delay
Dynamic Performance
Signal-To-Noise Ratio
(without Harmonics)
f
IN
= 50 MHz
f
IN
= 250 MHz
Total Harmonic Distortion
f
IN
= 50 MHz
f
IN
= 250 MHz
TEST
CONDITIONS
TEST
LEVEL
SPT7760A
MIN
TYP
MAX
8
SPT7760B
MIN
TYP MAX UNITS
8
Bits
f
CLK
= 100 kHz
f
CLK
= 100 kHz
I
I
-1.0
-0.85
Guaranteed
+1.0
+0.95
-1.5
-0.95
+1.5 LSB
+1.5 LSB
Guaranteed
V
RT
V
2.0 mA
kΩ
pF
MHz
MHz
+30 mV
+30 mV
V/ns
µA
80
30
Ω
MHz
GHz
ps
ps
1.9 ns
2.25 ns
V
IN
=0 V
Over Full Input Range
I
I
V
V
V
V
I
I
V
V
I
V
I
V
V
IV
IV
V
RB
.75
15
15
900
500
-30
-30
5
2
60
80
30
V
RT
2.0
V
RB
.75
15
15
900
500
+30
+30
-30
-30
5
2
60
1
2
250
1.4
1.75
1
2
250
1.4
1.75
0.9
1.25
1.9
2.25
0.9
1.25
I
I
I
I
45
43
-44
-36
43
41
-42
-34
dB
dB
dBc
dBc
SPT
SPT7760
2
3/10/97
ELECTRICAL SPECIFICATIONS
T
J
= T
C
= T
A
= +25
°C
, V
EE
=-5.2 V, V
RB
=-2.00 V, V
RM
=-1.0 V, V
RT
=0.00 V, f
clk
=1 GHz, Duty Cycle=50%, unless otherwise specified.
PARAMETERS
Dynamic Performance
Signal-to-Noise and Distortion
f
IN
= 50 MHz
f
IN
= 250 MHz
Spurious Free Dynamic Range
f
IN
= 50 MHz
f
IN
= 250 MHz
Digital Inputs
Input High Voltage
(CLK, NCLK)
Input Low Voltage
(CLK, NCLK)
Clock Pulse Width High (t
PWH
)
Clock Pulse Width Low (t
PWL
)
Digital Outputs
Logic "1" Voltage
Logic "0" Voltage
Rise Time
Fall Time
Power Supply Requirements
Voltage V
EE
Current I
EE
Power Dissipation
TEST
CONDITIONS
TEST
LEVEL
SPT7760A
MIN
TYP
MAX
SPT7760B
MIN
TYP MAX UNITS
I
I
I
I
42
35
47
39
40
33
43
35
dB
dB
dB
dB
I
I
I
I
I
I
V
V
IV
I
I
-1.1
-0.7
-1.8
0.4
0.4
-0.9
-1.8
450
450
-5.2
1.05
5.5
-1.5
-1.1
-0.7
-1.8
0.4
0.4
-0.9
-1.8
450
450
-5.2
1.05
5.5
V
-1.5 V
ns
ns
V
-1.5 V
ps
ps
-5.45 V
1.2 A
6.25 W
0.5
0.5
-1.1
0.5
0.5
-1.1
-1.5
20% to 80%
20% to 80%
-4.95
-5.45
1.2
6.25
-4.95
Typical Thermal Impedance:
θ
JC
= +4
°C/W.
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
Unless otherwise noted, all tests are pulsed
tests; therefore, T
J
= T
C
= T
A
.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
=25
°C,
and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at T
A
= 25
°C.
Parameter is
guaranteed over specified temperature range.
SPT
SPT7760
3
3/10/97
GENERAL DESCRIPTION
The SPT7760 is the fastest monolithic 8-bit parallel flash
A/D converter available today. The nominal conversion
rate is 1 GSPS and the analog bandwidth is in excess of
900 MHz. A major advance over previous flash converters
is the inclusion of 256 input preamplifiers between the
reference ladder and input comparators (see block dia-
gram). This not only reduces clock transient kickback to the
input and reference ladder due to a low AC beta but also
reduces the effect of the dynamic state of the input signal on
the latching characteristics of the input comparators. The
preamplifiers act as buffers and stabilize the input capaci-
tance so that it remains constant over different input voltage
and frequency ranges and therefore makes the part easier to
drive than previous flash converters. The preamplifiers also
add a gain of two to the input signal so that each comparator
has a wider overdrive or threshold range to "trip" into or out
of the active state. This gain reduces metastable states that
can cause errors at the output.
The SPT7760 has true differential analog and digital data
paths from the preamplifiers to the output buffers (Current
Mode Logic) for reducing potential missing codes while
rejecting common mode noise.
Signature errors are also reduced by careful layout of the
analog circuitry. The output drive capability of the device can
provide full ECL swings into 50
Ω
loads.
Figure 1 - SPT7760 Typical Interface Circuit
DRB
DRB
DRA
50
Ω
DRB (DATA READY)
U3
DRB (DATA READY)
DRA (DATA READY)
U3
50
Ω
V
IN
**
50
Ω
V
IN
V
IN
DRA
DRA (DATA READY)
-2.0 V Pulldown (Digital)
V
RTF
R
22
Ω
U1
V
RTS
D8B (OVR)
D7B (MSB)
D6B
D5B
D4B
D3B
D2B
D1B
D0B (LSB)
+
-
R
V
RM
*
22
Ω
2N2907
U1
V
RBS
V
RBF
50
Ω
50
Ω
Convert
U2
AGND
DGND
V
EE
SPT
+
-2.0 V
Reference
*
-5.2 V
D8A (OVR)
D7A (MSB)
D6A
D5A
D4A
D3A
D2A
D1A
D0A (LSB)
-
-5.2 V
CLK
NCLK
50
Ω
50
Ω
FB = Ferrite bead
.1 µF
-2.0 V
Pulldown
(Digital)
U1 = OP291 or equivalent with low offset/noise.
R = 1 kΩ; 0.1% matched.
= AGND
= DGND
U2 = Motorola ECLinPS Lite, MC10EL16, differential receiver.
U3 = MC10EL16 OR MC100EL16.
*
= 10 µF Tantalum Capacitor and 0.1 µF Chip Capacitor
-2 V
Pulldown
(Analog)
-5.2 V
*
FB
** = Care must be taken to avoid exceeding the maximum rating
for the input, especially during power up sequencing of the
analog input driver.
SPT7760
4
3/10/97
TYPICAL INTERFACE CIRCUIT
The circuit in figure 1 is intended to show the most elaborate
method of achieving the least error by correcting for integral
linearity, input induced distortion and power supply/ground
noise. This is achieved by the use of external reference
ladder tap connections, input buffer and supply decoupling.
Please contact the factory for the SPT7760 evaluation board
applications note that contains more details on interfacing the
SPT7760. The function of each pin and external connections
to other components is as follows:
V
EE
, AGND, DGND
V
EE
is the supply pin with AGND as ground for the device. The
power supply pins should be bypassed as close to the device
as possible with at least a .01
µF
ceramic capacitor. A 1
µF
tantalum can also be used for low frequency suppression.
DGND is the ground for the ECL outputs and is to be
referenced to the output pulldown voltage and appropriately
bypassed as shown in figure 5.
V
IN
(ANALOG INPUT)
There are two analog input pins that are tied to the same point
internally. Either one may be used as an analog input sense
and the other for input force. This is convenient for testing the
source signal to see if there is sufficient drive capability. The
pins can also be tied together and driven by the same source.
The SPT7760 is superior to similar devices due to a pream-
plifier stage before the comparators. This makes the device
easier to drive because it has constant capacitance and
induces less slew rate distortion.
CLK,
CLK
(CLOCK INPUTS)
The clock inputs are designed to be driven differentially with
ECL levels. The duty cycle of the clock should be kept at 50%
to avoid causing larger second harmonics. If this is not
important to the intended application, then duty cycles other
than 50% may be used.
D0 TO D8, DR, NDR (A AND B)
The digital outputs can drive 50
Ω
to ECL levels when pulled
down to -2 V. When pulled down to -5.2 V, the outputs can
drive 130
Ω
to 1 kΩ loads. All digital outputs are grey code with
the coding as shown in table 1. SPT recommends using
differential receivers on the outputs of the data ready lines to
ensure the proper output rise and fall times.
V
RBF
, V
RBS
, V
RTF
, V
RTS
, V
RM
(REFERENCE INPUTS)
There are two reference inputs and one external reference
voltage tap. These are -2 V (V
RB
force and sense), mid-tap
(V
RM
) and AGND (V
RT
force and sense). The reference pins
and tap can be driven by op amps as shown in figure 1 or V
RM
may be bypassed for limited temperature operation. These
voltage inputs can be bypassed to AGND for further noise
suppression if so desired.
Table I - Output Coding
VIN
> -0.5 LSB
-0.5 LSB
D8 D7
• • •
D0
1
1
0
0
0
•
•
•
0
0
•
•
•
0
0
0
10000000
10000000
10000000
10000000
10000001
•
•
•
11000000
01000000
•
•
•
00000001
00000000
00000000
-1.5 LSB
•
•
•
-1.0 V
•
•
•
-2.0 V+
1/2
LSB
< (-2.0 V +
1/2
LSB)
Indicates the transition between the two codes
THERMAL MANAGEMENT
The typical thermal impedance has been measured as fol-
lows:
ΘCA
= +17
°C/W
in still air with no heat sink
We highly recommend that a heat sink be used for this device
with adequate air flow to ensure rated performance of the
device. We have found that a Thermalloy 17846 heat sink
with a minimum air flow of 1 meter/second (200 linear feet per
minute) provides adequate thermal performance under labo-
ratory tests. Application specific conditions should be taken
into account to ensure that the device is properly heat sinked.
SPT
SPT7760
5
3/10/97
测试/测量
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