ADVANCE INFORMATION
DS3675-1·2
SP8790
60MHz44 (2-MODULUS EXTENDER)
4
The SP8790 is a divide-by-four counter designed for use
with 2-modulus dividers. It increases the minimum division
ratio of the 2-modulus divider while retaining the same difference
in division ratio. The device is suitable for use in low power
frequency synthesis interfacing to CMOS or TTL.
CLOCK INPUT
CLOCK INPUT
7 8
CONTROL INPUT
6
5 4
V
EE
NC
3
COUNTER OUTPUT
1
2
CONTROL OUTPUT
V
CC
FEATURES
s
Very Low Power
s
Control Input and Counter Output will Interface Directly
to TTL or CMOS
s
Interfaces to GPS SP8000 Series Programmable
2-Modulus Dividers
QUICK REFERENCE DATA
s
Supply Voltage: 5·0V
CM8
Fig. 1 Pin connections - bottom view
s
Power Consumption: 40mW
s
Temperature Range:
255°C
to
1125°C
(A Grade)
230°C
to
170°C
(B Grade)
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Open collector output voltage
Storage temperature range
Max. junction temperature
Max. clock input voltage
Output sink current
8V
12V
265°C
to
1150°C
1175°C
2·5V p-p
10mA
ORDERING INFORMATION
SP8790 A CM
SP8790 B CM
CONTROL
INPUT
6
CONTROL
OUTPUT
2
V
CC
1
D
Q
D
Q
OUTPUT
STAGE
3
OPEN COLLECTOR
COUNTER OUTPUT
D
Q
CK CK
D
Q
CK CK
8
CLOCK INPUT
7
CLOCK INPUT
5
V
EE
(0V)
NOTE:
NEGATIVE GOING OUTPUT
SHOULD CLOCK FOLLOWING STAGE
Fig. 2 Functional diagram
SP8790
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, the Electrical Characteristics are guaranteed over specified supply, frequency and temperature range
Supply voltage, V
CC
= 5V
±0·25V,
V
EE
= 0V
Temperature, T
AMB
=
255°C
to
1125°C
(A Grade),
230°C
to
170°C
(B Grade)
Value
Characteristic
Maximum frequency (sinewave input)
Power supply current
Control input high voltage
Control input low voltage
Output high voltage (pin 3)
Output low voltage (pins 3)
Output high voltage (pin 2)
Output low voltage (pin 2)
Clock to counter output
2ve
going delay
Clock to counter output
1ve
going delay
Clock to control output
2ve
going delay
Clock to control output
1ve
going delay
Control input to control output
2ve
going delay
Control input to control output
1ve
going delay
Symbol
f
MAX
I
CC
V
INH
V
INL
V
OH
V
OL
V
OH
V
OL
t
pHL
t
pLH
t
pHL
t
pLH
t
pHL
t
pLH
Min. Max.
60
3·5
0
9
4·27
3·28
11
10
1·5
0·4
4·5
3·7
25
40
15
26
12
16
Units
MHz
mA
V
V
V
V
V
V
ns
ns
ns
ns
ns
ns
Conditions
Tested as a controller, see Fig. 4
Notes
2
2
2
2
2
2
Pin 3 via 1·6kΩ to110V
Pin 3 via 1·6kΩ to110V
V
CC
= 5·2V (25°C)
V
CC
= 5·2V (25°C)
10kΩ pull-down on control output
10kΩ pull-down on control output
10kΩ pull-down on control output
10kΩ pull-down on control output
3
3
3, 4
3, 4
3, 4
3, 4
NOTES
1. The test configuration for dynamic testing is shown in Fig.4.
2. Tested at low and high temperatures only.
3. Guaranteed but not tested.
4. The propagation delays stated are with the device controlling the SP8695, which has internal 10kΩ pull-down resistors on its PE inputs. These
propagation delays will be reduced when the device is used with the SP8643/47 and SP8740 series of 2-modulus dividers, which have internal
4·3kΩ pull-downs. Refer to relevant data sheet/s.
CLOCK INPUT
CONTROL INPUT
COUNTER OUTPUT (PIN 3)
CONTROL OUTPUT (PIN 2)
N.B: IF CONTROL INPUT
=
‘1’ THEN CONTROL OUTPUT
=
‘1’
Fig. 3 Timing diagram
OPERATING NOTES
1. The device will normally be driven by capacitively coupling
the inputs to the outputs of a 2-modulus divider, as shown in
Figs. 4 and 5. The maximum frequency of the device when
used as a controller is limited by the internal delays to 60MHz.
However, when used as a
44
prescaler, it will operate at
frequencies in excess of 80MHz, the maximum frequency
being limited by saturation of the output stage.
2. The device is normally driven from very fast edges of a 2-
modulus divider, in which case there is no input slew rate
problem.
3. The control input is TTL/CMOS compatible.
4. The counter output (pin 3) interfaces to TTL/CMOS by the
addition of a pull-up resistor. For interfacing to CMOS, the
output can be connected with a pull-up resistor to a supply
which must not exceed 12V.
5. When used as a controller the device will self-oscillate in the
absence of an input signal; this can be prevented by connecting
a 47kΩ resistor from pin 7 to ground, as shown in Fig. 5.
6. The control output, which includes an internal 16kΩ pull-
down resistor, is ECL compatible and will interface directly to
ECL 2-modulus dividers such as the GPS SP8600 and SP8700
series as shown in Figs. 4 and 5.
2
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