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SN74AUC2G34
DUAL BUFFER GATE
www.ti.com
SCES514A – NOVEMBER 2003 – REVISED MARCH 2006
FEATURES
•
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
I
off
Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max t
pd
of 1.6 ns at 1.8 V
Low Power Consumption, 10
µA
at 1.8 V
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
•
•
•
•
•
•
•
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DRL PACKAGE
(TOP VIEW)
1A
GND
2A
1
2
3
6
5
4
1Y
1A
V
CC
2Y
GND
2A
1
2
3
6
5
4
YEP PACKAGE
(BOTTOM VIEW)
1Y
V
CC
2Y
1A
GND
2A
1
2
3
6
5
4
1Y
V
CC
2Y
2A
GND
1A
3
2
1
4
5
6
2Y
V
CC
1Y
DESCRIPTION/ORDERING INFORMATION
This dual buffer gate is operational at 0.8-V to 2.7-V V
CC
, but is designed specifically for 1.65-V to 1.95-V V
CC
operation.
The SN74AUC2G34 performs the Boolean function Y = A in positive logic.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
(1)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
–40°C to 85°C
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SOT-563 – DRL
SOT-23 – DBV
SC-70 – DCK
(1)
(2)
ORDERABLE PART NUMBER
SN74AUC2G34YEPR
Tape and reel
SN74AUC2G34YZPR
Tape and reel
Tape and reel
Tape and reel
SN74AUC2G34DRLR
SN74AUC2G34DBVR
SN74AUC2G34DCKR
U9_
U34_
U9_
_ _ _U9_
TOP-SIDE MARKING
(2)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
•
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2006, Texas Instruments Incorporated
SN74AUC2G34
DUAL BUFFER GATE
SCES514A – NOVEMBER 2003 – REVISED MARCH 2006
www.ti.com
FUNCTION TABLE
(EACH GATE)
INPUT
A
H
L
OUTPUT
Y
H
L
LOGIC DIAGRAM (POSITIVE LOGIC)
1A
1
6
1Y
2A
3
4
2Y
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
Supply voltage range
Input voltage range
(2)
Voltage range applied to any output in the high-impedance or power-off state
(2)
Output voltage range
(2)
Input clamp current
Output clamp current
Continuous output current
Continuous current through V
CC
or GND
DBV package
θ
JA
Package thermal impedance
(3)
DCK package
DRL package
YEP/YZP package
T
stg
(1)
(2)
(3)
Storage temperature range
–65
V
I
< 0
V
O
< 0
–0.5
–0.5
–0.5
–0.5
MAX
3.6
4.1
4.1
V
CC
+ 0.5
–50
–50
±20
±100
165
259
142
123
150
°C
°C/W
UNIT
V
V
V
V
mA
mA
mA
mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
2
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www.ti.com
SN74AUC2G34
DUAL BUFFER GATE
SCES514A – NOVEMBER 2003 – REVISED MARCH 2006
Recommended Operating Conditions
(1)
MIN
V
CC
V
IH
Supply voltage
V
CC
= 0.8 V
High-level input voltage
V
CC
= 1.1 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 0.8 V
V
IL
V
I
V
O
Low-level input voltage
Input voltage
Output voltage
V
CC
= 0.8 V
V
CC
= 1.1 V
I
OH
High-level output current
V
CC
= 1.4 V
V
CC
= 1.65 V
V
CC
= 2.3 V
V
CC
= 0.8 V
V
CC
= 1.1 V
I
OL
Low-level output current
V
CC
= 1.4 V
V
CC
= 1.65 V
V
CC
= 2.3 V
V
CC
= 0.8 V to 1.65 V
(2)
∆t/∆v
T
A
(1)
(2)
(3)
Input transition rise or fall rate
Operating free-air temperature
V
CC
= 1.65 V to 1.95 V
(3)
V
CC
= 2.3 V to 2.7 V
(3)
–40
V
CC
= 1.1 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
0
0
0.8
V
CC
0.65 × V
CC
1.7
0
0.35 × V
CC
0.7
3.6
V
CC
–0.7
–3
–5
–8
–9
0.7
3
5
8
9
20
20
10
85
°C
ns/V
mA
mA
V
V
V
V
MAX
2.7
UNIT
V
All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
The data was taken at C
L
= 15 pF, R
L
= 2 kΩ (see Figure 1).
The data was taken at C
L
= 30 pF, R
L
= 500
Ω
(see Figure 1).
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3
SN74AUC2G34
DUAL BUFFER GATE
SCES514A – NOVEMBER 2003 – REVISED MARCH 2006
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
I
OH
= –100
µA
I
OH
= –0.7 mA
V
OH
I
OH
= –3 mA
I
OH
= –5 mA
I
OH
= –8 mA
I
OH
= –9 mA
I
OL
= 100
µA
I
OL
= 0.7 mA
V
OL
I
OL
= 3 mA
I
OL
= 5 mA
I
OL
= 8 mA
I
OL
= 9 mA
I
I
I
off
I
CC
C
i
(1)
A inputs
V
I
= V
CC
or GND
V
I
or V
O
= 2.7 V
V
I
= V
CC
or GND,
V
I
= V
CC
or GND
All typical values are at T
A
= 25°C.
I
O
= 0
TEST CONDITIONS
V
CC
0.8 V to 2.7 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0.8 V to 2.7 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0 to 2.7 V
0
0.8 V to 2.7 V
2.5 V
2
0.25
0.3
0.4
0.45
0.6
±5
±10
10
µA
µA
µA
pF
V
0.8
1
1.2
1.8
0.2
MIN
V
CC
– 0.1
0.55
V
TYP
(1)
MAX
UNIT
Switching Characteristics
over recommended operating free-air temperature range, C
L
= 15 pF (unless otherwise noted) (see
Figure 1)
PARAMETER
t
pd
FROM
(INPUT)
A
TO
(OUTPUT)
Y
V
CC
= 0.8 V
TYP
6.4
V
CC
= 1.2 V
± 0.1 V
MIN
0.7
MAX
3.4
V
CC
= 1.5 V
± 0.1 V
MIN
0.6
MAX
2.3
V
CC
= 1.8 V
± 0.15 V
MIN
0.6
TYP
1
MAX
1.6
V
CC
= 2.5 V
± 0.2 V
MIN
0.5
MAX
1.2
ns
UNIT
Switching Characteristics
over recommended operating free-air temperature range, C
L
= 30 pF (unless otherwise noted) (see
Figure 1)
PARAMETER
t
pd
FROM
(INPUT)
A
TO
(OUTPUT)
Y
V
CC
= 1.8 V
± 0.15 V
MIN
0.7
TYP MAX
1.3
2.4
V
CC
= 2.5 V
± 0.2 V
MIN MAX
0.6
1.8
ns
UNIT
Operating Characteristics
T
A
= 25°C
PARAMETER
C
pd
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
V
CC
= 0.8 V
TYP
12
V
CC
= 1.2 V
TYP
12
V
CC
= 1.5 V
TYP
12
V
CC
= 1.8 V
TYP
13
V
CC
= 2.5 V
TYP
14
UNIT
pF
4
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