W320-03
200 MHz Spread Spectrum Clock Synthesizer/Driver
with Differential CPU Outputs
Features
• Compliant with Intel
®
CK-Titan Clock Synthe-
sizer/Driver Specifications
• Multiple output clocks at different frequencies
• Three pairs of differential CPU outputs, up to 200 MHz
• Ten synchronous PCI clocks, three free-running
• Six 3V66 clocks
• Two 48 MHz clocks
• One reference clock at 14.318 MHz
• One VCH clock
• Spread Spectrum clocking (down spread)
• Power-down features (PCI_STOP#, CPU_STOP#
PWR_DWN#)
• Three Select inputs (Mode select & IC Frequency
Select)
• OE and Test Mode support
• 56-pin SSOP package and 56-pin TSSOP package
Benefits
• Supports next-generation Pentium
®
processors using
differential clock drivers
• Motherboard clock generator
• Support Multiple CPUs and a chipset
• Support for PCI slots and chipset
• Supports AGP, DRCG reference and Hub Link
• Supports USB host controller and graphic controller
• Supports ISA slots and I/O chip
• Enables reduction of electromagnetic interference
(EMI) and overall system cost
• Enables ACPI-compliant designs
• Supports up to four CPU clock frequencies
• Enables ATE and “bed of nails” testing
• Widely available, standard package enables lower cost
Logic Block Diagram
VDD_REF
PWR
Pin Configurations
SSOP & TSSOP
Top View
VDD_REF
XTAL_IN
XTAL_OUT
GND_REF
PCI_F0
PWR
Stop
Clock
Control
X1
X2
XTAL
OSC
REF
1
2
3
4
5
6
7
8
9
10
11
56
55
54
53
52
51
50
49
48
47
46
REF
S1
S0
CPU_STOP#
CPU0
CPU#0
VDD_CPU
CPU1
CPU#1
GND_CPU
VDD_CPU
CPU2
CPU#2
MULT0
IREF
GND_IREF
S2
USB
DOT
VDD_ 48 MHz
GND_ 48 MHz
3V66_1/VCH
PCI_STOP#
3V66_0
VDD_3V66
GND_3V66
SCLK
SDATA
PLL Ref Freq
PLL 1
S0:2
PWR_GD#
CPU_STOP#
Divider
Network
VDD_CPU
CPU0:2
CPU#0:2
PCI_F1
PCI_F2
VDD_PCI
GND_PCI
PCI0
PCI1
PCI2
PCI3
VDD_PCI
Gate
PWR
Stop
Clock
Control
VDD_PCI
PCI_F0:2
PCI0:6
W320-03
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI_STOP#
/2
PWR_DWN#
VDD_3V66
3V66_0
PWR
PWR
GND_PCI
PCI4
PCI5
PCI6
VDD_3V66
GND_3V66
66BUFF0/3V66_2
66BUFF1/3V66_3
66BUFF2/3V66_4
66IN/3V66_5
PWR_DWN#
VDD_CORE
GND_CORE
PWR_GD#
3V66_2:4/
66BUFF0:2
3V66_5/ 66IN
PLL 2
VDD_48MHz
PWR
USB (48MHz)
DOT (48MHz)
VCH_CLK/ 3V66_1
SDATA
SCLK
SMBus
Logic
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 16
www.SpectraLinear.com
W320-03
Pin Summary
Name
REF
XTAL_IN
XTAL_OUT
CPU, CPU# [0:2]
3V66_0
3V66_1/VCH
66IN/3V66_5
66BUFF [2:0] /3V66
[4:2]
PCI_F [0:2]
PCI [0:6]
USB
DOT
S2
S1, S0
IREF
MULT0
PWR_DWN#
PCI_STOP#
CPU_STOP#
PWRGD#
Pins
56
2
3
Description
3.3V 14.318 MHz clock output
14.318 MHz crystal input
14.318 MHz crystal input
44, 45, 48, 49, 51,
Differential CPU clock outputs
52
33
35
24
21, 22, 23
5, 6, 7,
3.3V 66 MHz clock output
3.3V selectable through SMBus to be 66 MHz or 48 MHz
66 MHz input to buffered 66BUFF and PCI or 66 MHz clock from internal VCO
66 MHz buffered outputs from 66Input or 66 MHz clocks from internal VCO
33 MHz clocks divided down from 66Input or divided down from 3V66
10, 11, 12, 13, 16,
PCI clock outputs divided down from 66Input or divided down from 3V66
17, 18
39
38
40
54, 55
42
43
25
34
53
28
Fixed 48 MHz clock output
Fixed 48 MHz clock output
Special 3.3V 3 level input for Mode selection
3.3V LVTTL inputs for CPU frequency selection
A precision resistor is attached to this pin which is connected to the internal
current reference
3.3V LVTTL input for selecting the current multiplier for the CPU outputs
3.3V LVTTL input for Power_Down# (active LOW)
3.3V LVTTL input for PCI_STOP# (active LOW)
3.3V LVTTL input for CPU_STOP# (active LOW)
3.3V LVTTL input is a level sensitive strobe used to determine when S[2:0] and
MULTI0 inputs are valid and OK to be sampled (Active LOW).
Once PWRGD#
is sampled LOW, the status of this output will be ignored.
SMBus compatible SDATA
SMBus compatible Sclk
SDATA
SCLK
29
30
VDD_REF, VDD_PCI, 1, 8, 14, 19, 32, 46,
3.3V power supply for outputs
VDD_3V66,
50
VDD_CPU
VDD_48 MHz
VDD_CORE
37
26
3.3V power supply for 48 MHz
3.3V power supply for PLL
GND_REF, GND_PCI, 4, 9, 15, 20, 31, 36,
Ground for outputs
GND_3V66,
41, 47
GND_IREF,
VDD_CPU
GND_CORE
27
Ground for PLL
Rev 1.0, November 25, 2006
Page 2 of 16
W320-03
Function Table
S2
1
1
1
1
0
0
0
0
Mid
Mid
Mid
Mid
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
S0
[1]
CPU
(MHz)
66 MHz
100 MHz
200 MHz
133 MHz
66 MHz
100 MHz
200 MHz
133 MHz
Hi-Z
TCLK/2
Reserved
Reserved
3V66[0:1] 66BUFF[0:2]/3 66IN/3V66_5
(MHz)
V66[2:4] (MHz)
(MHz)
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
Hi-Z
TCLK/4
Reserved
Reserved
66 IN
66 IN
66 IN
66 IN
66 MHz
66 MHz
66 MHz
66 MHz
Hi-Z
TCLK/4
Reserved
Reserved
66 MHz Input
66 MHz Input
66 MHz Input
66 MHz Input
66 MHz
66 MHz
66 MHz
66 MHz
Hi-Z
TCLK/4
Reserved
Reserved
PCI_F/PCI
(MHz)
66 IN/2
66 IN/2
66 IN/2
66 IN/2
33 MHz
33 MHz
33 MHz
33 MHz
Hi-Z
TCLK/8
Reserved
Reserved
REF0(MHz)
USB/DOT
(MHz)
Notes
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
1, 5
6, 7, 8
–
–
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
Hi-Z
TCLK
Reserved
Reserved
Hi-Z
TCLK/2
Reserved
Reserved
Swing Select Functions
Mult0
0
1
Board Target
Trace/Term Z
60
50
Reference R, IREF
=
V
DD
/(3*Rr)
Rr = 221 1%,
IREF = 5.00 mA
Rr = 475 1%,
IREF = 2.32 mA
Output
Current
I
OH
= 4*IREF
I
OH
= 6*IREF
V
OH
@ Z
1.0V @ 50
0.7V @ 50
Clock Driver Impedances
Impedance
Minimum
Buffer Name
CPU, CPU#
REF
PCI, 3V66, 66BUFF
USB
DOT
3.135–3.465
3.135–3.465
3.135–3.465
3.135–3.465
V
DD
Range
Buffer Type
Type X1
Type 3
Type 5
Type 3A
Type 3B
20
12
12
12
50
40
30
30
30
60
55
55
55
Typical
Maximum
Clock Enable Configuration
PWR_DWN# CPU_STOP# PCI_STOP#
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
CPU
IREF*2
IREF*2
IREF*2
ON
ON
CPU#
FLOAT
FLOAT
FLOAT
ON
ON
3V66
LOW
ON
ON
ON
ON
66BUFF
LOW
ON
ON
ON
ON
PCI_F
LOW
ON
ON
ON
ON
PCI
LOW
OFF
ON
OFF
ON
USB/DOT
LOW
ON
ON
ON
ON
VCOS/
OSC
OFF
ON
ON
ON
ON
Notes:
1. TCLK is a test clock driven in on the XTALIN input in test mode.
2. “Normal” mode of operation.
3. Range of reference frequency allowed is min. = 14.316 nominal = 14.31818 MHz, max = 14.32 MHz.
4. Frequency accuracy of 48 MHz must be +167PPM to match USB default.
5. Mid is defined a Voltage level between 1.0V and 1.8V for 3 level input functionality. Low is below 0.8V. High is above 2.0V.
6. TCLK is a test clock over driven on the XTAL_IN input during test mode.
7. Required for DC output impedance verification.
8. These modes are to use the SAME internal dividers as the CPU = 200-MHz mode. The only change is to slow down the internal VCO to allow under clock
margining.
Rev 1.0, November 25, 2006
Page 3 of 16
W320-03
Serial Data Interface (SMBus)
To enhance the flexibility and function of the clock synthesizer,
a two signal SMBus interface is provided according to the
SMBus specification. Through the Serial Data Interface (SDI),
various device functions such as individual clock output
buffers, etc can be individually enabled or disabled. W320-03
support both block read and block write operations.
The registers associated with the SDI initialize to their default
setting upon power-up, and therefore use of this interface is
optional. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power
management functions.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte, (most significant bit first) with the
ability to stop after any complete byte has been transferred.
Indexed bytes are not allowed.
A block write begins with a slave address and a WRITE
condition. The R/W bit is used by the SMBus controller as a
data direction bit. A zero indicates a WRITE condition to the
clock device. The slave receiver address is 11010010 (D2h).
A command code of 0000 0000 (00h) and the byte count bytes
are required for any transfer. After the command code, the
core logic issues a byte count which describes number of
additional bytes required for the transfer, not including the
command code and byte count bytes. For example, if the host
has 20 data bytes to send, the first byte would be the number
20 (14h), followed by the 20 bytes of data. The byte count byte
is required to be a minimum of one byte and a maximum of 32
bytes It may not be 0.
Figure 1
shows an example of a block
write.
A transfer is considered valid after the acknowledge bit corre-
sponding to the byte count is read by the controller.
Start Slave Address R/W
bit 1 1 0 1 0 0 1 0 0/1
1 bit
7 bits
1
A
Command
Code
00000000
8 bits
A Byte Count = A Data Byte 0 A
N
1
8 bits
1
8 bits
1
...
Data Byte N-1 A Stop
bit
8 bits
1
1 bit
1
From Master to Slave
From Slave to Master
Figure 1. An Example of a Block Write
Data Byte Configuration Map
Data Byte 0: Control Register (0 = Enable, 1 = Disable)
Bit
Bit 7
Affected Pin#
5, 6, 7, 10, 11,
12, 13, 16, 17,
18, 33, 35
–
35
44, 45, 48, 49,
51, 52
10, 11, 12, 13,
16, 17, 18
–
–
–
Name
PCI [0:6]
CPU[2:0]
3V66[1:0]
TBD
3V66_1/VCH
CPU [2:0]
CPU# [2:0]
PCI [6:0]
–
–
–
Description
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
TBD
VCH Select 66 MHz/48 MHz
0 = 66 MHz, 1 = 48 MHz
CPU_STOP#
Reflects the current value of the external CPU_STOP# pin
PCI_STOP#
(Does not affect PCI_F [2:0] pins)
S2
Reflects the value of the S2 pin sampled on Power-up
S1
Reflects the value of the S1 pin sampled on Power-up
S0
Reflects the value of the S1 pin sampled on Power-up
Type
R/W
Power On
Default
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R/W
R
R/W
R
R
R
0
0
N/A
N/A
N/A
N/A
N/A
Rev 1.0, November 25, 2006
Page 4 of 16
W320-03
Data Byte 1
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
–
–
44, 45
48, 49
51, 52
44, 45
48, 49
51, 52
N/A
N/A
CPU2
CPU2#
CPU1
CPU1#
CPU0
CPU0#
CPU2
CPU2#
CPU1
CPU1#
CPU0
CPU0#
Name
CPU Mult0 Value
TBD
Allow Control of CPU2 with assertion of CPU_STOP#
0 = Not free running; 1 = Free running
Allow Control of CPU1 with assertion of CPU_STOP#
0 = Not free running;1 = Free running
Allow Control of CPU0 with assertion of CPU_STOP#
0= Not free running; 1 = Free running
CPU2 Output Enable
1 = Enabled; 0 = Disabled
CPU1Output Enable
1 = Enabled; 0= Disabled
CPU0 Output Enable
1 = Enabled; 0 = Disabled
Description
Type
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Power On
Default
N/A
0
0
0
0
1
1
1
Data Byte 2
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
–
18
17
16
13
12
11
10
N/A
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
Name
N/A
PCI6 Output Enable
1 = Enabled; 0 = Disabled
PCI5 Output Enable
1 = Enabled; 0 = Disabled
PCI4 Output Enable
1 = Enabled; 0 = Disabled
PCI3 Output Enable
1 = Enabled; 0 = Disabled
PCI2 Output Enable
1 = Enabled; 0 = Disabled
PCI1 Output Enable
1 = Enabled; 0 = Disabled
PCI0 Output Enable
1 = Enabled; 0 = Disabled
Pin Description
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power On
Default
0
1
1
1
1
1
1
1
Data Byte 3
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
38
39
7
6
5
7
6
5
DOT
USB
PCI_F2
PCI_F1
PCI_F0
PCI_F2
PCI_F1
PCI_F0
Name
Pin Description
DOT 48-MHz Output Enable
USB 48-MHz Output Enable
Allow control of PCI_F2 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
Allow control of PCI_F1 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
Allow control of PCI_F0 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
PCI_F2 Output Enable
PCI_F1Output Enable
PCI_F0 Output Enable
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power On
Default
1
1
0
0
0
1
1
1
Rev 1.0, November 25, 2006
Page 5 of 16
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