W311
FTG for VIA™ Pro-266 DDR Chipset
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum Technology
• System frequency synthesizer for VIA Pro-2000
• Programmable clock output frequency with less than 1
MHz increment
• Integrated fail-safe Watchdog Timer for system
recovery
• Automatically switch to HW selected or SW
programmed clock frequency when Watchdog Timer
time-out
• Capable of generate system RESET after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
• Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable drive strength for CPU and PCI output
clocks
• Programmable output skew between CPU, AGP and PCI
• Supports Intel
®
Celeron
®
and Pentium
®
III class
processor
• Three copies of CPU output
• Nine copies of PCI output
• One 48 MHz output for USB
• One 24 MHz or 48 MHz output for SIO
• Two buffered reference outputs
• Three copies of APIC output
• Supports frequencies up to 200MHz
• SMBus Interface for programming
• Power management control inputs
• Available in 48-pin SSOP
Key Specifications
CPU Cycle-to-cycle Jitter: .......................................... 250 ps
CPU to CPU Output Skew........................................... 175 ps
PCI Cycle-to-cycle Jitter: ............................................. 500 ps
PCI to PCI Output Skew:............................................. 500 ps
Block Diagram
Pin Configuration
[1]
Note:
1. Signals marked with * have internal pull-up resistors
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 18
www.SpectraLinear.com
W311
Pin Definitions
Pin Name
RST#
CPU1:3
Pin No.
32
39, 38, 35
Pin
Type
O
(open
drain)
O
I
O
Pin Description
System Reset Output:
Open-drain system reset output.
CPU Clock Output:
Frequency is set by the FS0:4 input or through serial input
interface. The CPU1:3 outputs are gated by the CLK_STOP# input.
CPU Output Control:
3.3V LVTTL-compatible input that stop CPU1:3.
PCI Clock Outputs 1 through 8:
Frequency is set by FS0:4 inputs or through
serial input interface; see
Table 5
for details. PCI1:8 outputs are gated by the
PCI_STOP# input.
PCI_STOP# Input:
3.3V LVTTL-compatible input that stops PCI1:8.
Free-Running PCI Clock Output:
Frequency is set by FS0:4 inputs or through
serial input interface; see
Table 5
for details.
Frequency Selection Inputs:
Selects CPU clock frequency as shown in
Table 1.
AGP Clock Output:
This pin serves as the select strap to determine device
operating frequency as described in
Table 5.
APIC Clock Output:
APIC clock outputs.
48 MHz Output/Frequency Select 3:
48 MHz is provided in normal operation.
In standard PC systems, this output can be used as the reference for the Universal
Serial Bus host controller. This pin also serves as a power-on strap option to
determine device operating frequency as described in
Table 5.
24_48 MHz Output/Frequency Select 2:
In standard PC systems, this output
can be used as the clock input for a Super I/O chip. The output frequency is
controlled by Configuration Byte 3 bit[6]. The default output frequency is 24 MHz.
This pin also serves as a power-on strap option to determine device operating
frequency as described in
Table 5.
Reference Clock Output 1/Frequency Select 4:
3.3V 14.318 MHz output clock.
This pin also serves as a power-on strap option to determine device operating
frequency as described in
Table 5.
Reference Clock Output 0:
3.3V 14.318 MHz output clock.
Clock pin for SMBus circuitry.
Data pin for SMBus circuitry.
Crystal Connection or External Reference Frequency Input:
This pin has dual
functions. It can be used as an external 14.318 MHz crystal connection or as an
external reference frequency input.
Crystal Connection:
An input connection for an external 14.318 MHz crystal. If
using an external reference, this pin must be left unconnected.
Power Connection:
Power supply for core logic, PLL circuitry, PCI outputs,
reference outputs, 48 MHz output, and 24-48 MHz output, connect to 3.3V supply.
CPU_STOP#
PCI1:8
34
10, 11, 13,
14, 16, 17,
18, 20
33
9
21, 22
23, 26, 27
45, 44, 42
6
PCI_STOP#
PCI_F
FS0:1
AGP0:2
APIC0:2
48MHz/FS3
O
O
I
O
O
I/O
24_48MHz/
FS2
REF1/FS4
7
47
I/O
I/O
REF0
SCLK
SDATA
X1
48
28
29
3
O
I
I/O
I
X2
VDD_REF,
VDD_48MHz,
VDD_PCI,
VDD_AGP,
VDD_CORE
VDD_CPU,
VDD_APIC
41
1, 5,15, 24,
31
I
P
41, 46, 37
P
Power Connection:
Power supply for APIC and CPU output buffers, connect to
2.5V.
Rev 1.0, November 25, 2006
Page 2 of 18
W311
Serial Data Interface
The W311 features a two-pin, serial data interface that can be
used to configure internal register settings that control
particular device functions.
Data Protocol
The clock driver serial protocol supports byte/word write,
byte/word read, block write and block read operations from the
Table 1.
Bit
7
6:0
Descriptions
0 = Block read or block write operation
1 = Byte/Word read or byte/word write operation
Byte offset for byte/word read or write operation. For block read or write operations, these bits
need to be set at ‘0000000’.
controller. For block write/read operation, the bytes must be
accessed in sequential order from lowest to highest byte with
the ability to stop after any complete byte has been trans-
ferred. For byte/word write and byte read operations, system
controller can access individual indexed byte. The offset of the
indexed byte is encoded in the command code.
The definition for the command code is defined in
Table 2.
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
...
...
...
...
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 0 – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data Byte N/Slave Acknowledge...
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
...
...
...
...
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Not Acknowledge
Stop
Block Read Protocol
Description
Rev 1.0, November 25, 2006
Page 3 of 18
W311
Table 3. Word Read and Word Write Protocol
Word Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte or word operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
Data byte low – 8 bits
Acknowledge from slave
Data byte high –- 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte or word operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Data byte low from slave – 8 bits
Acknowledge
Data byte high from slave – 8 bits
NOT acknowledge
Stop
Word Read Protocol
Description
19
20:27
28
29:36
37
38
19
20
21:27
28
29
30:37
38
39:46
47
48
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
Byte Read Protocol
Description
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Rev 1.0, November 25, 2006
Page 4 of 18
W311
W311 Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 0: Control Register 0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
–
–
–
–
–
–
–
–
Name
Reserved
SEL2
SEL1
SEL0
FS_Override
SEL4
SEL3
Reserved
Default
0
0
0
0
0
1
0
0
Reserved
See
Table 5
See
Table 5
See
Table 5
0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings
See
Table 5
See
Table 5
Reserved
Description
2. All unused register bits (reserved and N/A) should be
written to a “0” level.
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization.
Byte 1: Control Register 1
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Pin#
-
-
-
-
Name
Reserved
Spread Select2
Spread Select1
Spread Select0
Default
0
0
0
0
Reserved
‘000’ = Normal (spread off)
‘001’ = Test Mode
‘010’ = Reserved
‘011’ = Three-Stated
‘100’ = –0.5%
‘101’ = ± 0.5%
‘110’ = ± 0.25%
‘111’ = ± 0.38%
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Description
Bit 3
Bit 2
Bit 1
Bit 0
Byte 2: Control Register 2
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
35
38
39
42
CPU3
CPU2
CPU1
APIC2
1
1
1
1
Pin#
20
18
17
16
14
13
11
10
PC8
PCI7
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
Name
Default
1
1
1
1
1
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Description
Rev 1.0, November 25, 2006
Page 5 of 18
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