DC Output Current, per Pin ......................–25 mA to +25 mA
DC Input Voltage
[2]
.........................................–3.0V to +7.0V
DC Program Voltage .................................................. +13.0V
Operating Range
Range
Commercial
Industrial
Military
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
–55
°
C to +125
°
C (Case)
V
CC
5V
±5%
5V
±10%
5V
±10%
Electrical Characteristics
Over the Operating Range
[3]
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC1
I
CC2
t
R
t
F
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
Input Current
Output Leakage Current
Output Short Circuit Current
Power Supply
Current (Standby)
Power Supply Current
Recommended Input Rise Time
Recommended Input Fall Time
GND
≤
V
IN
≤
V
CC
V
O
= V
CC
or GND
V
CC
= Max., V
OUT
= 0.5V
[4, 5]
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8 mA
Min.
2.4
Max.
0.45
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
ns
ns
2.2
–0.3
–10
–40
–30
Commercial
Military/Industrial
V
I
= V
CC
or GND (No Load)
f = 1.0 MHz
[4,6]
Commercial
Military/Industrial
V
CC
+0.3
0.8
+10
+40
–90
150
170
200
220
100
100
V
I
= V
CC
or GND (No Load)
Capacitance
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 2V, f = 1.0 MHz
V
OUT
= 2.0V, f = 1.0 MHz
Max.
10
10
Unit
pF
pF
AC Test Loads and Waveforms
[7]
5V
OUTPUT
50 pF
INCLUDING
JIGAND
SCOPE
Equivalent to:
R2
250Ω
R1 464Ω
5V
OUTPUT
5 pF
R2
250Ω
R1 464Ω
ALL INPUT PULSES
3.0V
GND
≤
6ns
90%
10%
t
f
90%
10%
≤
6ns
t
R
(a)
(b)
C344–4
t
F
C344–5
THÉVENIN EQUIVALENT (commercial/military)
163Ω
OUTPUT
1.75V
C344–6
Notes:
2. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –2.0V for periods less than 20 ns.
3. Typical values are for T
A
= 25°C and V
CC
= 5V.
4. Guaranteed by design but not 100% tested.
5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
OUT
= 0.5V has been chosen to avoid
test problems caused by tester ground degradation.
6. Measured with device programmed as a 16-bit counter.
7. Part (a) in AC Test Load and Waveforms is used for all parameters except t
ER
and t
XZ
, which is used for part (b) in AC Test Load and Waveforms. All external timing
parameters are measured referenced to external pins of the device.
2
CY7C344
CY7C344B
Timing Delays
Timing delays within the CY7C344/CY7C344B may be easily
determined using
Warp2®, Warp2Sim™,
or
Warp3®
software
or by the model shown in
Figure 1.
The CY7C344/CY7C344B
has fixed internal delays, allowing the user to determine the
worst case timing delays for any design. For complete timing
information, the
Warp3
software provides a timing simulator.
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
EXP
to t
S1
. Determine which of
1/(t
WH
+ t
WL
), 1/t
CO1
, or 1/(t
EXP
+ t
S1
) is the lowest frequency. The
lowest of these frequencies is the maximum data-path frequency for
the synchronous configuration.
When calculating external asynchronous frequencies, use
t
AS1
if all inputs are on dedicated input pins. If any data is applied to
an I/O pin, t
AS2
must be used as the required set-up time. If (t
AS2
+
t
AH
) is greater than t
ACO1
, 1/(t
AS2
+ t
AH
) becomes the limiting fre-
quency in the data-path mode unless 1/(t
AWH
+ t
AWL
) is less than
1/(t
AS2
+ t
AH
).
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
EXP
to t
AS1
. Determine which
of 1/(t
AWH
+ t
AWL
), 1/t
ACO1
, or 1/(t
EXP
+ t
AS1
) is the lowest frequency.
The lowest of these frequencies is the maximum data-path frequency
for the asynchronous configuration.
The parameter t
OH
indicates the system compatibility of this device
when driving other synchronous logic with positive input hold times,
which is controlled by the same synchronous clock. If t
OH
is greater
than the minimum required input hold time of the subsequent syn-
chronous logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case environmental
and supply voltage conditions.
The parameter t
AOH
indicates the system compatibility of this de-
vice when driving subsequent registered logic with a positive hold
time and using the same clock as the CY7C344/CY7C344B.In gen-
eral, if t
AOH
is greater than the minimum required input hold time of
the subsequent logic (synchronous or asynchronous), then the devic-
es are guaranteed to function properly under worst-case environ-
mental and supply voltage conditions, provided the clock signal
source is the same. This also applies if expander logic is used in the
clock signal path of the driving device, but not for the driven device.
This is due to the expander logic in the second device’s clock signal
path adding an additional delay (t
EXP
), causing the output data from
the preceding device to change prior to the arrival of the clock signal
at the following device’s register.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this datasheet is not implied. Exposure to absolute maximum
ratings conditions for extended periods of time may affect de-
vice reliability. The CY7C344/CY7C344B contains circuitry to
protect device pins from high-static voltages or electric fields;
however, normal precautions should be taken to avoid applying
any voltage higher than maximum rated voltages.
For proper operation, input and output pins must be con-
strained to the range GND
≤
(VIN or VOUT)
≤
VCC. Unused in-
puts must always be tied to an appropriate logic level (either VCC or
GND). Each set of VCC and GND pins must be connected together
directly at the device. Power supply decoupling capacitors of at least
0.2
µF
must be connected between VCC and GND. For the most
effective decoupling, each VCC pin should be separately decoupled.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum ex-
pander delay t
EXP
to the overall delay.
When calculating synchronous frequencies, use t
S1
if all inputs
are on the input pins. t
S2
should be used if data is applied at an I/O
pin. If t
S2
is greater than t
CO1
, 1/t
S2
becomes the limiting frequency
in the data-path mode unless 1/(t
WH
+ t
WL
) is less than 1/t
S2
.
EXPANDER
DELAY
t
EXP
LOGIC ARRAY
CONTROLDELAY t
CLR
t
LAC
t
PRE
INPUT
DELAY
t
IN
LOGIC ARRAY t
RSU
DELAY
t
RH
t
LAD
SYSTEM CLOCK DELAYt
ICS
I/O
I/O DELAY
t
IO
CLOCK
DELAY
t
IC
REGISTER
OUTPUT
DELAY
OUTPUT
t
COMB
t
LATCH
t
RD
t
OD
t
XZ
t
ZX
INPUT
I/O
FEEDBACK
DELAY
t
FD
C344–7
Figure 1. CY7C344/CY7C344B Timing Model
3
CY7C344
CY7C344B
External Synchronous Switching Characteristics
[7]
Over Operating Range
7C344B–10
Parameter
t
PD1
t
PD2
t
PD3
t
PD4
t
EA
t
ER
t
CO1
t
CO2
t
S
t
H
t
WH
t
WL
t
RW
t
RR
t
RO
t
PW
t
PR
t
PO
t
CF
t
P
f
MAX1
Description
Dedicated Input to Combinatorial Output Delay
I/O Input to Combinatorial Output Delay
[9]
Dedicated Input to Combinatorial Output Delay
with Expander Delay
[10]
I/O Input to Combinatorial Output Delay with
Expander Delay
[4, 11]
Input to Output Enable
Delay
[4]
[8]
7C344B–12
Min.
Max.
12
12
12
12
18
18
18
18
12
12
12
12
6
6
12
12
8
8
0
0
4.5
4.5
4.5
4.5
12
12
12
12
7C344–15
7C344B–15
Min.
Max.
15
15
15
15
30
30
30
30
20
20
20
20
10
10
20
20
10
10
0
0
6
6
6
6
20
20
20
20
ns
15
15
20
20
20
20
ns
15
15
4
4
13
13
50.0
50.0
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
Min.
Com’l /Ind
Mil
Com’l/Ind
Mil
Com’l /Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l /Ind
Mil
Com’l /Ind
Mil
Com’l /Ind
Mil
Com’l/Ind
Mil
0
4
4
10
10
Mil
6
Max.
10
10
16
16
10
10
5
10
Input to Output Disable Delay
[4]
Synchronous Clock Input to Output Delay
Synchronous Clock to Local Feedback to Com-
binatorial Output
[4, 12]
Dedicated Input or Feedback Set-Up Time to
Synchronous Clock Input
Input Hold Time from Synchronous Clock Input
[7]
Com’l /Ind
Synchronous Clock Input HIGH
Time
[4]
Com’l/Ind
Mil
Synchronous Clock Input LOW Time
[4]
Asynchronous Clear
Width
[4]
Com’l /Ind
Mil
Com’l /Ind
Mil
Asynchronous Clear Recovery Time
[4]
Asynchronous Clear to Registered Output De-
lay
[4]
Asynchronous Preset Width
[4]
Asynchronous Preset Recovery
Time
[4]
Com’l /Ind
Mil
Com’l /Ind
Mil
Com’l /Ind
Mil
Com’l /Ind
Mil
Asynchronous Preset to Registered Output
Delay
[4]
Synchronous Clock to Local Feedback
Input
[4, 13]
Com’l /Ind
Mil
Com’l /Ind
Mil
External Synchronous Clock Period (1/f
MAX3
)
[4]
External Maximum
Frequency(1/(t
CO1
+ t
S
))
[4, 14]
Com’l/Ind
Mil
Com’l/Ind
Mil
10
10
10
10
3
8
90.9
9
9
71.4
71.4
12
12
12
12
12
12
12
12
3
3
Shaded area contains preliminary information.
4
CY7C344
CY7C344B
External Synchronous Switching Characteristics
[7]
Over Operating Range (continued)
7C344B–10
Parameter
f
MAX2
f
MAX3
f
MAX4
t
OH
Description
Maximum Frequency with Internal Only Feed-
back (1/(t
CF
+ t
S
))
[4, 15]
Data Path Maximum Frequency, least of 1/(t
WL
+ t
WH
), 1/(t
S
+ t
H
), or (1/t
CO1
)
[4, 16]
Maximum Register Toggle Frequency 1/(t
WL
+
t
WH
)
[4, 17]
Output Data Stable Time from Synchronous
Clock Input
[4, 18]
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/ Ind
Mil
3
125.0
125.0
Min.
111.1
Max.
7C344B–12
Min.
90.9
90.9
111.1
111.1
111.1
111.1
3
3
Max.
7C344–15
7C344B–15
Min.
71.4
71.4
83.3
83.3
83.3
83.3
3
3
ns
MHz
MHz
Max.
Unit
MHz
Shaded area contains preliminary information.
Notes:
8. This parameter is the delay from an input signal applied to a dedicated input pin to a combinatorial output on any output pin. This delay assumes no expander
terms are used to form the logic function.
9. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to
form the logic function.
10. This parameter is the delay associated with an input signal applied to a dedicated input pin to combinatorial output on any output pin. This delay assumes
expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter
is tested periodically by sampling production material.
11. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output pin. This delay assumes expander terms are used
to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by
sampling production material.
12. This specification is a measure of the delay from synchronous register clock input to internal feedback of the register output signal to a combinatorial output
for which the registered output signal is used as an input. This parameter assumes no expanders are used in the logic of the combinatorial output and the
register is synchronously clocked. This parameter is tested periodically by sampling production material.
13. This specification is a measure of the delay associated with the internal register feedback path. This delay plus the register set-up time, t
S
, is the minimum
internal period for an internal state machine configuration. This parameter is tested periodically by sampling production material.
14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external only feedback can operate.
15. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states
must also control external points, this frequency can still be observed as long as it is less than 1/t
CO1
. This specification assumes no expander logic is used. This
parameter is tested periodically by sampling production material.
16. This frequency indicates the maximum frequency at which the device may operate in data-path mode (dedicated input pin to output pin). This assumes that
no expander logic is used.
17. This specification indicates the guaranteed maximum frequency in synchronous mode, at which an individual output or buried register can be cycled by a
clock signal applied to either a dedicated input pin or an I/O pin.
18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
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