1CY 7C23 5A
CY7C235A
1K x 8 Registered PROM
Features
• CMOS for optimum speed/power
• High speed
— 18 ns address set-up
— 12 ns clock to output
• Low power
— 495 mW (commercial)
— 660 mW (military)
• Synchronous and asynchronous output enables
• On-chip edge-triggered registers
• Programmable asynchronous registers (INIT)
• EPROM technology, 100% programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP or 28-pin
LCC and PLCC
•
5V
±10%
V
CC
, commercial and military
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static dis-
charge
Functional Description
The CY7C235A is a high-performance 1024 word by 8 bit elec-
trically programmable read only memory packaged in a slim
300-mil plastic or hermetic DIP, 28-pin leadless chip carrier, or
28-pin plastic leaded chip carrier. The memory cells utilize
proven EPROM floating gate technology and byte-wide intelli-
gent programming algorithms.
The CY7C235A replaces bipolar devices pin for pin and offers
the advantages of lower power, superior performance, and
high programming yield. The EPROM cell requires only 12.5V
for the supervoltage, and low current requirements allow for
gang programming. The EPROM cells allow for each memory
location to be tested 100%, as each location is written into,
erased, and repeatedly exercised prior to encapsulation. Each
PROM is also tested for AC performance to guarantee that the
product will meet AC specification limits after customer pro-
gramming.
Logic Block Diagram
INIT
O
7
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CP
CP
O
0
COLUMN
ADDRESS
ADDRESS
DECODER
ROW
ADDRESS
PROGRAMMABLE
ARRAY
MUL
TIPLEXER
O
5
8-BIT
EDGE-
TRIGGERED
REGISTER
O
4
O
3
O
2
O
1
O
6
Pin Configuration
DIP
Top View
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
8
A
9
E
INIT
E
S
CP
O
7
O
6
O
5
O
4
O
3
C235A-2
LCC/PLCC
Top View
E
S
E
C235A-1
A
4
A
3
A
2
A
1
A
0
NC
O
0
4 3 2 1 28 27 26
25
5
24
6
23
7
22
8
21
9
20
10
19
11
12 1314151617 18
E
INIT
E
S
CP
NC
O
7
O
6
C235A-3
Selection Guide
Minimum Address Set-Up Time (ns)
Maximum Clock to Output (ns)
Maximum Operating
Commercial
Current (mA)
Military
7C235A-18
18
12
90
7C235A-25
25
12
90
120
7C235A-30
30
15
90
120
7C235A-40
40
20
90
120
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose •
CA 95134 •
408-943-2600
November 1992 – Revised March 1995
CY7C235A
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... −65°C
to +150°C
Ambient Temperature with
Power Applied..................................................
−55°C
to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12 for DIP)
.................................. −
0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
.................................................... −
0.5V to +7.0V
DC Input Voltage
.................................................−3.0V
to +7.0V
DC Program Voltage (Pins 7, 18, 20 for DIP) ............... 13.0V
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
[1]
Military
[2]
Ambient
Temperature
0
°
C to +70
°
C
−40
°
C to +85
°
C
−
55
°
C to +125
°
C
V
CC
5V
±10%
5V
±10%
5V
±10%
Electrical Characteristics
Over Operating Range
[3]
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
V
CD
I
OZ
I
OS
I
CC
V
PP
I
PP
V
IHP
V
ILP
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
Input Leakage Current
Input Clamp Diode Voltage
Output Leakage Current
Output Short Circuit Current
Power Supply Current
Programming Supply Voltage
Programming Supply Current
Input HIGH Programming Voltage
Input LOW Programming Voltage
3.0
0.4
Test Conditions
V
CC
= Min., I
OH
=
−4.0
mA
V
IN
= V
IH
or V
IL
V
CC
= Min., I
OL
= 16 mA
V
IN
= V
IH
or V
IL
Guaranteed Input Logical HIGH Voltage for All
Inputs
[4]
Guaranteed Input Logical LOW Voltage for All
Inputs
[4]
GND < V
IN
< V
CC
Note 5
GND < V
OUT
< V
CC
Output Disabled
[4]
V
CC
= Max., V
OUT
= 0.0V
[6]
I
OUT
= 0 mA,
V
CC
= Max.
Commercial
Military
12
−10
−20
+10
−90
90
120
13
50
V
mA
V
V
µA
mA
mA
−10
2.0
0.8
+10
Min.
2.4
0.4
Max.
Unit
V
V
V
V
µA
Capacitance
[5]
Parameter
C
IN
C
OUT
Notes:
1.
2.
3.
4.
5.
6.
a
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
=5.0V
Max.
10
10
Unit
pF
pF
Contact a Cypress representative for industrial temperature range specifications.
T
A
is the “instant on” case temperature.
See the last page of this specification for Group A subgroup testing information.
For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
See Introduction to CMOS PROMs in this Data Book for general information on testing.
For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
2
CY7C235A
AC Test Loads and Waveforms
[5]
5V
OUTPUT
50pF
INCLUDING
JIGAND
SCOPE
R2
167Ω
R1 250Ω
5V
OUTPUT
5 pF
INCLUDING
JIGAND
SCOPE
R2
167Ω
3.0V
GND
≤
5 ns
C235A-4
R1 250Ω
ALL INPUT PULSES
90%
10%
90%
10%
≤
5 ns
C235A-5
(a) Normal Load
Equivalent to:
(b) High Z Load
TH
ÉVENIN EQUIVALENT
100Ω
2.0V
C235A-6
OUTPUT
Operating Modes
The CY7C235A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
provided with synchronous (E
S
) and asynchronous (E) output
enables and asynchronous initialization (INIT).
Upon power-up, the synchronous enable (ES) flip-flop will be
in the set condition causing the outputs (O
0
−
O
7
) to be in the
OFF or high-impedance state. Data is read by applying the
memory location to the address input (A
0
−
A
9
) and a logic
LOW to the enable (E
S
) input. The stored data is accessed and
loaded into the master flip-flops of the data register during the
address set-up time. At the next LOW-to-HIGH transition of the
clock (CP), data is transferred to the slave flip-flops, which
drive the output buffers, and the accessed data will appear at
the outputs (O
0
−
O
7
), provided the asynchronous enable (E)
is also LOW.
The outputs may be disabled at any time by switching the
asynchronous enable (E) to a logic HIGH, and may be re-
turned to the active state by switching the enable to a logic
LOW.
Regardless of the condition of E, the outputs will go to the OFF
or high-impedance state upon the next positive clock edge af-
ter the synchronous enable (E
S
) input is switched to a HIGH
level. If the synchronous enable pin is switched to a logic LOW,
the subsequent positive clock edge will return the output to the
active state if E is LOW. Following a positive clock edge, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
LOW-to-HIGH transition of the clock. This unique feature al-
lows the CY7C235A decoders and sense amplifiers to access
the next location while previously addressed data remains sta-
ble on the outputs.
System timing is simplified in that the on-chip edge-triggered
register allows the PROM clock to be derived directly from the
system clock without introducing race conditions. The on-chip
register timing requirements are similar to those of discrete
registers available in the market.
The CY7C235A has an asynchronous initialize input (INIT).
The initialize function is useful during power-up and time-out
sequences and can facilitate implementation of other sophis-
ticated functions such as a built-in “jump start” address. When
activated the initialize control input causes the contents of a
user programmed 1025th 8-bit word to be loaded into the
on-chip register. Each bit is programmable and the initialize
function can be used to load any desired combination of 1s
and 0s into the register. In the unprogrammed state, activating
INIT will generate a register CLEAR (all outputs LOW). If all
the bits of the initialize word are programmed, activating INIT
performs a register PRESET (all outputs HIGH).
Applying a LOW to the INIT input causes an immediate load of
the programmed initialize word into the master and slave
flip-flops of the register, independent of all other inputs, includ-
ing the clock (CP). The initialize data will appear at the device
outputs after the outputs are enabled by bringing the asyn-
chronous enable (E) LOW.
When power is applied the (internal) synchronous enable
flip-flop will be in a state such that the outputs will be in the
high-impedance state. In order to enable the outputs, a clock
must occur and the ES input pin must be LOW at least a set-up
time prior to the clock LOW-to-HIGH transition. The E input
may then be used to enable the outputs.
When the asynchronous initialize input, INIT, is LOW, the data
in the initialize byte will be asynchronously loaded into the out-
put register. It will not, however, appear on the output pins until
they are enabled, as described in the preceding paragraph.
3
CY7C235A
Switching Characteristics
Over Operating Range
[3, 5]
7C235A-18
Parameter
t
SA
t
HA
t
CO
t
PWC
t
SES
t
HES
t
DI
t
RI
t
PWI
t
COS
t
HZC
t
DOE
t
HZE
Notes:
7. Applies only when the synchronous (E
S
) function is used.
7C235A-25
Min.
25
0
Max.
7C235A-30
Min.
30
0
Max.
7C235A-40
Min.
40
0
Max.
Unit
ns
ns
20
20
15
5
ns
ns
ns
ns
35
20
25
ns
ns
ns
25
25
25
25
ns
ns
ns
ns
Description
Address Set-Up to Clock HIGH
Address Hold from Clock HIGH
Clock HIGH to Valid Output
Clock Pulse Width
E
S
Set-Up to Clock HIGH
E
S
Hold from Clock HIGH
Delay from INIT to Valid Output
INIT Recovery to Clock HIGH
INIT Pulse Width
Inactive to Valid Output from Clock HIGH
[7]
Inactive Output from Clock HIGH
[7]
Valid Output from E LOW
Inactive Output from E HIGH
Min.
18
0
Max.
12
12
10
5
20
15
15
15
15
15
15
20
20
12
10
5
12
15
10
5
25
20
20
20
20
20
20
15
25
20
20
20
20
Switching Waveforms
[5]
t
HA
A
0
−
A
10
t
SES
t
HES
t
SES
t
HES
t
SA
t
HA
E
S
t
SES
t
HES
CP
t
PWC
t
PWC
t
PWC
t
PWC
t
PWC
t
PWC
O
0
−
O
7
t
CO
t
HZC
t
COS
t
CO
t
HZE
t
DOE
E
t
DI
INIT
t
PWI
C235A-7
t
RI
Programming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software pack-
ages, please see the PROM Programming Information located
at the end of this section. Programming algorithms can be ob-
tained from any Cypress representative.
4
CY7C235A
Table 1. Mode Selection.
Pin Function
[8]
Read or Output Disable
Mode
Read
Output Disable
Output Disable
Initialize
Program
Program Verify
Program Inhibit
Intelligent Program
Program Initialize Byte
Blank Check
Notes:
8. X = “don’t care” but not to exceed V
CC
±5%.
DIP
Top View
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
0
D
1
D
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
8
A
9
E
V
PP
VFY
PGM
D
7
D
6
D
5
D
4
D
3
C235A-8
A
0
, A
3
−
A
9
A
0
, A
3
−
A
9
A
0
, A
3
−
A
9
A
0
, A
3
−
A
9
A
0
, A
3
−
A
9
A
0
, A
3
−
A
9
A
0
, A
3
−
A
9
A
0
, A
3
−
A
9
A
0
, A
3
−
A
9
A
0
, A
3
−
A
9
A
0
, A
3
−
A
9
A
0
, A
3
−
A
9
A
1
A
1
A
1
A
1
A
1
A
1
A
1
A
1
A
1
A
1
V
PP
A
1
A
2
A
2
A
2
A
2
A
2
A
2
A
2
A
2
A
2
A
2
V
ILP
A
2
CP
PGM
X
X
X
X
V
ILP
V
IHP
V
IHP
V
ILP
V
ILP
V
IHP
E
S
VFY
V
IL
V
IH
X
X
V
IHP
V
ILP
V
IHP
V
IHP
V
IHP
V
ILP
E
E
V
IL
X
V
IH
V
IL
V
IHP
V
IHP
V
IHP
V
IHP
V
IHP
V
IHP
INIT
V
PP
V
IH
V
IH
V
IH
V
IL
V
PP
V
PP
V
PP
V
PP
V
PP
V
PP
O
7
−
O
0
D
7
−
D
0
O
7
−
O
0
High Z
High Z
Init Byte
D
7
−
D
0
O
7
−
O
0
High Z
D
7
−
D
0
D
7
−
D
0
Zeros
Other
LCC/PLCC
Top View
A
4
A
3
A
2
A
1
A
0
NC
D
0
5
6
7
8
9
10
11
4 3 2 1 28 27 26
25
24
23
22
21
20
19
121314151617 18
E
V
PP
VFY
PGM
NC
D
7
D
6
C235A-9
Figure 1. Programming Pinouts.
5
ARM技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
