CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
18-Mbit DDR-II SRAM 4-Word
Burst Architecture
Features
• 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
• 300-MHz clock for high bandwidth
• 4-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces
(data transferred at 600MHz) @ 300 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–V
DD
)
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Offered in both lead-free and non-lead free packages
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Functional Description
The CY7C1317BV18, CY7C1917BV18, CY7C1319BV18, and
CY7C1321BV18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II (Double Data Rate) architecture. The
DDR-II consists of an SRAM core with advanced synchronous
peripheral circuitry and a two-bit burst counter. Addresses for
Read and Write are latched on alternate rising edges of the
input (K) clock. Write data is registered on the rising edges of
both K and K. Read data is driven on the rising edges of C and
C if provided, or on the rising edge of K and K if C/C are not
provided. Each address location is associated with four 8-bit
words in the case of CY7C1317BV18 and four 9-bit words in
the case of CY7C1917BV18 that burst sequentially into or out
of the device. The burst counter always starts with “00” inter-
nally in the case of CY7C1317BV18 and CY7C1917BV18. On
CY7C1319BV18 and CY7C1321BV18, the burst counter
takes in the last two significant bits of the external address and
bursts four 18-bit words in the case of CY7C1319BV18, and
four 36-bit words in the case of CY7C1321BV18, sequentially
into or out of the device.
Asynchronous inputs include output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need for
separately capturing data from each individual DDR-II SRAM
in the system design. Output data clocks (C/C) enable
maximum system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Configurations
CY7C1317BV18 – 2M x 8
CY7C1917BV18 – 2M x 9
CY7C1319BV18 – 1M x 18
CY7C1321BV18 – 512K x 36
Selection Guide
300 MHz
Maximum Operating Frequency
Maximum Operating Current
300
550
278 MHz
278
530
250 MHz
250
500
200 MHz
200
450
167 MHz
167
400
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 38-05622 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 27, 2006
stm32/stm8
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