The CY2V9950 is a low-voltage, low-power, eight-output,
200-MHz clock driver. It features functions necessary to
optimize the timing of high performance computer and
communication systems.
The user can program the output banks through 3F[0:1] and
4F[0:1]pins. Any one of the outputs can be connected to
feedback input to achieve different reference frequency multi-
plication and divide ratios and zero input-output delay.
The device also features split output bank power supplies
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the PE pin controls the synchro-
nization of the output signals to either the rising or the falling
edge of the reference clock.
Block Diagram
Pin Configuration
TEST
PE
FS VDDQ 1
VSS
TEST
VDD
REF
2F1
3F0
R EF
3
3
PLL
FB
32 31 30 29 28 27 26 25
3F1
1Q 0
4F0
4F1
PE
VDDQ4
4Q1
4Q0
VSS
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
VDDQ3
3Q1
VSS
VDD
3Q0
2Q1
2Q0
FB
FS
2F0
24
23
22
1F1
1F0
sOE#
VDDQ1
1Q0
1Q1
VSS
VSS
21
20
19
18
17
1F1:0
1Q 1
CY2V9950
2Q 0
2F1:0
2Q 1
3F1:0
3
3
/K
3Q 0
3Q 1
VDDQ 3
4F1:0
3
3
/M
4Q 0
4Q 1
VDDQ 4 sO E#
Cypress Semiconductor Corporation
Document #: 38-07436 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised August 11, 2004
CY2V9950
Pin Definitions
Pin
29
13
27
22
Name
REF
FB
TEST
sOE#
I, PD
I/O
[1]
Type
I
LVTTL/LVCMOS
I
LVTTL
3-Level
I
2-Level
Description
Reference Clock Input.
Feedback Input.
When MID or HIGH, disables PLL (except for conditions of note 3).
REF goes to all outputs. Set LOW for normal operation.
Synchronous Output Enable.
When HIGH, it stops clock outputs (except
2Q0 and 2Q1) in a LOW state (for PE = H or M) – 2Q0 and 2Q1 may be
used as the feedback signal to maintain phase lock. When TEST is held at
MID level and sOE# is high, the nF[1:0] pins act as output disable controls
for individual banks when nF[1:0] = LL. Set sOE# LOW for normal
operation.
Selects Positive or Negative Edge Control and High or Low output
drive strength.
When LOW / HIGH the outputs are synchronized with the
negative/positive edge of the reference clock. Please see
Table 5.
Select frequency of the outputs.
Please see
Tables 1
and
2.
Selects VCO operating frequency range.
Please see
Table 4.
Four banks of two outputs.
Please see
Tables 1
and
2
for frequency
settings.
Power supply for Bank 1 and Bank 2 output buffers.
Please see
Table 6
for supply level constraints
Power supply for Bank 3 output buffers.
Please see
Table 6
for supply
level constraints
Power supply for Bank 4 output buffers.
Please see
Table 6
for supply
level constraints
Power supply for internal circuitry.
Please see
Table 6
for supply level
constraints
Ground.
The divider settings, output frequencies, and possible config-
urations of connecting FB to ANY output are summarized in
Table 3.
Table 3. Output Frequency Settings
Configuration
FB to
1Qn, 2Qn
3Qn
4Qn
1Q, 2Q
[6]
F
REF
K x F
REF
M x F
REF
Output Frequency
3Q
(1/K) x F
REF
F
REF
(M/K) x F
REF
4Q
(1/M) x F
REF
(K/M) x F
REF
F
REF
4
PE
I, PU
I
I
O
PWR
PWR
PWR
PWR
PWR
LVTTL
24, 23, 26,
25, 1, 32, 3, 2
31
19, 20, 15,
16,10,11, 6,
7
21
12
5
14,30
8, 9, 17, 18,
28
nF[1:0]
FS
nQ[1:0]
VDDQ1
[2]
VDDQ3
[2]
VDDQ4
[2]
VDD
[2]
VSS
3-Level
3-Level
LVTTL
Power
Power
Power
Power
Power
Device Configuration
The outputs of the CY2V9950 can be configured to run at
frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output
dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in
Table 1
and
2
respectively.
Table 1. Output Divider Settings – Bank 3
3F[1:0]
LL
[4]
HH
Other
K – Bank3 Output Divider
2
4
1
Table 2. Output Divider Settings – Bank 4
4F[1:0]
LL
[4]
HH
Other
M – Bank4 Output Divider
2
Inverted
[5]
1
The 3-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY2V9950 PLL operating frequency range that
corresponds to each FS level is given in
Table 4.
Notes:
1. ‘PD’ indicates an internal pull-down and ‘PU’ indicates an internal pull-up. ‘3’ indicates a three-level input buffer.
2. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. The 1F[0:1]
and 2F[0:1] pins should be either tied to mid-level or left floating (on-chip resistors will bias to mid-level) during normal operation.
4. LL disables outputs if TEST = MID and sOE# = HIGH.
5. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE = HIGH, sOE# disables them LOW when PE = LOW.
6. These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the VCO operating frequency at a given
reference frequency (F
REF
) and divider and feedback configurations. The user must select a configuration and a reference frequency that will generate a VCO
frequency that is within the range specified by FS pin. Refer to
Table 4.
Document #: 38-07436 Rev. *A
Page 2 of 9
CY2V9950
Table 4. Frequency Range Select
FS
L
M
H
PLL Frequency Range
24 to 50 MHz
48 to 100 MHz
96 to 200 MHz
Table 6. Power Supply Constraints
VDD
3.3V
2.5V
VDDQ1
[7]
3.3V or 2.5V
2.5V
VDDQ3
[7]
3.3V or 2.5V
2.5V
VDDQ4
[7]
3.3V or 2.5V
2.5V
Governing Agencies
The following agencies provide specifications that apply to the
CY2V9950. The agency name and relevant specification is
listed below.
Agency Name
JEDEC
IEEE
UL-194_V0
MIL
Specification
JESD 51 (Theta JA)
JESD 65 (Skew, Jitter)
1596.3 (Jiter Specs)
94 (Moisture Grading)
883E Method 1012.1 (Therma Theta JC)
The PE pin determines whether the outputs synchronize to the
rising edge or the falling edge of the reference signal, as
indicated in
Table 5.
Table 5. PE Settings
PE
L
H
Synchronization
Negative
Positive
The CY2V9950 features split power supply buses for Banks 1
and 2, Bank 3 and Bank 4, which enables the user to obtain
both 3.3V and 2.5V output signals from one device. The core
power supply (VDD) must be set a level which is equal or
higher than that on any one of the output power supplies.
Absolute Maximum Conditions
Parameter
V
DD
V
DD
V
IN(MIN)
V
IN(MAX)
T
S
T
A
T
J
ESD
HBM
Ø
JC
Ø
JA
UL-94
MSL
F
IT
Parameter
V
DD
V
IL
V
IH
V
IHH[8]
V
IMM[8]
V
ILL[8]
I
IL
Description
Operating Voltage
Operating Voltage
Input Voltage
Input Voltage
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
ESD Protection (Human Body Model)
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Flammability Rating
Moisture Sensitivity Level
Failure in Time
Manufacturing Testing
Condition
Functional @ 2.5V ± 5%
Functional @ 3.3V ± 10%
Relative to V
SS
Relative to V
DD
Non Functional
Functional
Functional
MIL-STD-883, Method 3015
Mil-Spec 883E Method 1012.1
JEDEC (JESD 51)
@1/8 in.
Min.
2.25
2.97
V
SS
– 0.3
–
–65
–40
–
2000
42
105
V–0
1
10
ppm
Max.
2.75
3.63
–
V
DD
+ 0.3
+150
+85
155
–
Unit
V
V
V
V
°C
°C
°C
V
°C/W
°C/W
DC Electrical Specifications @ 2.5V
Description
2.5 Operating Voltage
Input LOW Voltage
Input HIGH Voltage
Input HIGH Voltage
Input MID Voltage
Input LOW Voltage
Input Leakage Current
3-Level Inputs
(TEST, FS, nF[1:0])
(These pins are normally wired to
VDD,GND or unconnected)
V
IN
= V
DD
/G
ND
,V
DD
= Max
(REF, PE, and FB inputs)
2.5V ± 5%
REF, FB, PE, and sOE# Inputs
Conditions
Min.
2.375
–
1.7
V
DD
– –0.4
V
DD
/2–0.2
–
–5
Max.
2.625
0.7
–
–
V
DD
/2 +
0.2
0.4
5
Unit
V
V
V
V
V
V
µA
Notes:
7. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g., VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3
= 2.5V and VDDQ4 = 2.5V.
8. These Inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2.
Skew between the nominal output rising edge to the
inverted output falling edge
Skew between non-inverted outputs running at
different frequencies
Skew between nominal to inverted outputs running
at different frequencies
Skew between nominal outputs at different power
supply levels
Skew between the outputs of any two devices under
identical settings and conditions (VDDQ, VDD, temp,
air flow, frequency, etc.)
Condition
Min.
6
200
0.25
–
–
–
–
–
–
–
–
–250
45
–
–
0.15
–
–
–
Max.
200
400
3.5
150
200
200
500
500
500
650
750
+250
55
1.5
2.0
1.5
0.5
100
150
Unit
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
ns
ns
ns
ms
ps
ps
Notes:
9. Test Load = 20 pF, terminated to VCC/2. All outputs are equally loaded.
10. t
PD
is measured at 1.5V for VDD = 3.3V and at 1.25V for VDD = 2.5V with REF rise/fall times of 0.5ns between 0.8V–2.0V.
11. t
LOCK
is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits.
12. Lock detector circuit may be unreliable for input frequencies lower than 4MHz, or for input signals which contain significant jitter.
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