• Supports LVTTL switching levels on the RESET pin
• Output drivers have controlled edge rates, so no
external resistors are required
• Two KV ESD protection
• Latch-up performance exceeds 100 mA: JESD78, Class II
• Conforms to JEDEC STD (JESD82-3) for buffered DDR
DIMMs
• 48-pin TSSOP
When RESET is LOW, the differential input receivers are
disabled, and undriven (floating) data, clock, and REF voltage
inputs are allowed. In addition, when RESET is LOW, all
registers are reset and all outputs force to the LOW state. The
LVCMOS RESET input must always be held at a valid logic
HIGH or LOW level.
To ensure defined outputs from the register before a stable
clock has been supplied, RESET must be held in the LOW
state during power-up.
In the DDR registered DIMM application, RESET is specified
to be completely asynchronous with respect to CLK and CLK.
Therefore, no timing relationship can be guaranteed between
the two. When entering reset, the register will be cleared and
the outputs will be driven LOW quickly, relative to the time to
disable the differential input receivers, thus ensuring no
glitches on the output. However, when coming out of reset, the
register will become active quickly, relative to the time to
enable the differential input receivers. As long as the data
inputs are low, and the clock is stable during the time from the
LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design must ensure that the outputs will
remain LOW.
Description
This 14-bit registered buffer is designed specifically for 2.3V to
2.7V V
DD
operation and is characterized for operation from
0°C to + 85°C.
All inputs are compatible with the JEDEC Standard for
SSTL_2, except the LVCMOS reset (RESET) input. All outputs
are SSTL_2, Class II-compatible.
The SSTV16857 operates from a differential clock (CLK and
CLK). Data is measured at the crossing of CLK going HIGH,
and CLK going LOW.
Block Diagram
Pin Configuration
Q1
Q2
VSS
VDDQ
Q3
Q4
Q5
VSS
VDDQ
Q6
Q7
VDDQ
VSS
Q8
Q9
VDDQ
VSS
Q10
Q11
Q12
VDDQ
VSS
Q13
Q14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D1
D2
VSS
VDD
D3
D4
D5
D6
D7
CLK
CLK
VDD
VSS
VREF
RESET
D8
D9
D10
D11
D12
VDD
VSS
D13
D14
RESET
CLK
CLK
VREF
D1
1D
C1
R
Q1
To 13 Other Channels
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
CY2SSTV16857
Page 1 of 7
www.SpectraLinear.com
CY2SSTV16857
Pin Description
Pin
34
3,8,13,17,22,27,36,46
28, 37, 45
1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19,
20, 23, 24
25, 26, 29, 30, 31, 32, 33, 40, 41,
42, 43, 44, 47, 48
39, 38
4, 8, 12, 16, 21
35
Name
RESET
VSS
VDD
Q(1:14)
D(1:14)
CLK, CLK
VDDQ
VREF
I/O
I
Ground
Power
O
I
I/I
Power
I
Ground.
2.5V nominal supply voltage.
Data outputs, SSTL_2, Class II output.
Data input clocked on the crossing of the rising edge
of CLK, and the falling edge of CLK.
Differential clock input.
Power supply voltage quiet, 2.5V nominal.
Input reference voltage, 1.25V nominal.
Type
Description
Rev 1.0, November 21, 2006
Page 2 of 7
CY2SSTV16857
Absolute Maximum Conditions
[1, 2, 3]
This device contains circuitry designed to protect the inputs
against damage due to high static voltages or electric field;
however, precautions should be taken to avoid application of
any voltage higher than the maximum rated voltages to this
circuit. For proper operation, V
in
and V
out
should be
constrained to the range:
Parameter
V
DD
V
DD
V
in
V
out
I
OUT
I
IK
I
OK
I
DD/
I
SS
LU
I
R
PS
T
s
T
a
T
j
Ø
Jc
Ø
JA
UL
FL
MSL
ESD
h
Supply Voltage
[4]
Operating Voltage
[4]
Input Voltage
Output Voltage
DC Output Current
Continuous Clamp Current
Continuous Clamp Current
Continuous current through each V
DD
or V
SS
Latch Up Immunity
Power Supply Ripple
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Flammability
Moisture Sensitivity
ESD Protection (Human Body Model)
Exceeds spec of
Ripple Frequency < 100 kHz
Non-functional
Functional
Functional
Mil-Spec 883E Method 1012.1
JEDEC (JESD 51)
By design and verification
By design and verification
2000
22.23
74.52
V–0
MSL – 1
–65
0
100
150
+150
+70
165
V
I
< 0 or V
I
> V
SS
V
O
< 0
Description
V
SS
< (V
in
or V
out
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
Condition
Non-functional
Functional
Relative to V
SS
Relative to V
SS
Min.
2.3
2.3
0
Max.
2.7
2.7
V
DD
V
DDQ
±50
±50
–50
±100
Unit
VDC
VDC
VDC
VDC
mA
mA
mA
mA
mA
mVp-p
°C
°C
°C
°C/W
°C/W
Grade
Grade
V
Table 1. DC Electrical Specifications
(V
DD
= Temperature = 0°C to +85 °C)
Parameter
V
DD
V
DDQ
V
REF
V
TT
V
IH
V
IL
V
OL
Supply Voltage
Description
PC1600,2100,2700
PC3200
Condition
Min.
2.5
2.5
1.25
V
REF
–
40 mV
RESET
RESET
V
DD
/V
DDQ
= 2.3V to 2.7V, I
OL
=
100 A, V
DD
= 2.3 to 2.7V
V
DD
/V
DDQ
= 2.3V, I
OL
= 16 mA,
V
DD
= 2.3V
1.7
0.7
0.2
0.35
Typ.
2.6
2.6
1.3
Max.
2.7
2.7
1.35
Unit
V
V
V
V
V
V
V
Output Supply Voltage PC1600,2100,2700
PC3200
Reference voltage
(V
REF
= V
DDQ
/2)
Termination voltage
Input Voltage, High
Input Voltage, Low
Output Voltage, Low
PC1600,2100,2700
PC3200
V
REF
V
REF
+4
0 mV
Notes:
1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
2. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended period may affect reliability.
3. All terminals except V
DD
.
4. V
DD
/V
DDQ
terminals.
Rev 1.0, November 21, 2006
Page 3 of 7
CY2SSTV16857
Table 1. DC Electrical Specifications
(V
DD
= Temperature = 0°C to +85 °C) (continued)
Parameter
V
OH
Description
Output Voltage, High
Condition
V
DD
/V
DDQ
= 2.3V to 2.7V, I
OH
=
–100 A, V
DD
=2.3 to 2.7V
V
DD
/V
DDQ
= 2.3V, I
OH
= –16 mA
I
IL
Input Current
Data Inputs
V
I
= 1.7V or 0.8V, V
REF
= 1.15V or
1.35V, V
DD
= 2.7V
V
I
= 2.7V or 0,V
REF
= 1.15V or
1.35V, V
DD
= 2.7V
V
I
= 1.7V or 0.8V, V
REF
= 1.15V or
1.35V, V
DD
= 3.6V
V
I
= 2.7V or 0
CLK, CLK
V
I
= 1.7V or 0.8V, V
REF
= 1.15V or
1.35V
V
I
= 2.7V or 0, V
REF
= 1.15V or
1.35V, V
dd
= 2.7V
RESET
VREF
I
IH
I
DD
Input Current, High
Dynamic Supply Current
V
I
= V
DD
or V
SS
, V
DD
= 2.7V
V
I
= 1.5V or 1.35V, V
DD
= 2.7
Data inputs only
V
I
= 1.7V or 0.8V, I
O
= 0, V
DD
=
2.7V
V
I
= 2.7V or 0, I
O
= 0, V
DD
= 2.7V
C
in
Input pin capacitance
RESET
Clock and Data Inputs
L
pin
Pin Inductance
All
V
I
= 1.7V or 0.8V, I
O
= 0, V
DD
=
2.7V
2.5
2.1
3
2.7
3.5
4.5
pF
pF
nH
90
90
±5
±5
±5
±5
±1
±1
±5
±5
A
A
A
A
A
A
A
A
mA.
mA
mA
Min.
V
DD
–
0.2
1.95
Typ.
Max.
Unit
V
Table 2. AC Input Electrical Specifications
(V
DD
= 2.5 VDC ± 5%, Temperature = 0°C to +85°C)
V
DD
= 2.5V ± 0.2V
Parameter
F
IN
P
W
T
ACT
T
INACT
T
SET
Description
Input Clock Frequency
Pulse Duration
Differential Inputs Active Time
CLK, CLK
CLK, CLK HIGH or LOW
Data inputs must be LOW after RESET HIGH
3.3
22
22
0.75
0.9
0.75
0.9
360
Condition
Min.
Max.
200
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
mV
Differential Inputs Inactive Time Data and clock inputs must be held at valid levels (not
floating) after RESET LOW
Set-up Time
Fast slew rate, (see notes 5 and 7), Data before CLK,
CLK
Slow slew rate, (see notes 6 and 7), Data before CLK,
CLK
T
HOLD
I
Vpp
Hold Time
Input Voltage, Pk–Pk
Fast slew rate, (see notes 5 and 7), Data after CLK, CLK
Slow slew rate (see notes 6 and 7), Data after CLK, CLK
Notes:
5. For data signal input slew rate > 1 V/ns.
6. For data signal input slew rate > 0.5 V/ns and < 1 V/ns.
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