Preliminary
Features
F
131072 x 8 bit static CMOS RAM
F
35 and 55 ns Access Time
F
Common data inputs and
F
F
UL62H1708A
Low Voltage Automotive Fast 128K x 8 SRAM
Description
The UL62H1708A is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-Transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the active state (E1 = L and
E2 = H) each address change
leads to a new Read or Write cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
G, afterwards the data word will be
available at the outputs DQ0-DQ7.
After the address change, the data
outputs go High-Z until the new
information is available. The data
outputs have no preferred state. If
the memory is driven by CMOS
levels in the active state, and if
there is no change of the address,
data input and control signals W or
G, the operating current (I
O
= 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of E2 or W, or by the rising
edge of E1, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E1
and E2, all inputs consist of NOR
gates, so that no pull-up/pull-down
resistors are required.
F
F
F
F
F
F
F
F
data outputs
Three-state outputs
Typ. operating supply current
35 ns: 45mA
55 ns: 30mA
Standby current <100µA at 125°C
TTL/CMOS-compatible
Power supply voltage 3.3 V
Operating temperature range
-40 °C to 85 °C
-40 °C to 125 °C
CECC 90000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity >100 mA
Package: SOP32 (300/330 mil)
Pin Configuration
Pin Description
n.c.
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
VCC
A15
E2
W
A13
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A16
DQ0 - DQ7
E1
E2
G
W
VCC
VSS
n.c.
Signal Description
Address Inputs
Data In/Out
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
not connected
SOP
25
24
23
22
21
20
19
18
17
Top View
November 01, 2001
1
UL62H1708A
Block Diagram
A7
A8
A9
A4
A11
A12
A13
A14
A15
A16
A0
A1
A2
A3
A10
A5
A6
Row Address
Inputs
Row Decoder
Memory Cell
Array
1024 Rows x
128 x 8 Columns
Preliminary
Column Address
Inputs
Column Decoder
DQ0
Common Data I/O
Sense Amplifier/
Write Control Logic
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Address
Change
Detector
Clock
Generator
Truth Table
Operating Mode
Standby/not selected
E1
*
H
Internal Read
Read
Write
* H or L
V
CC
V
SS
E1
E2
W
G
E2
L
*
H
H
H
W
*
*
H
H
L
G
*
*
H
L
*
DQ0 - DQ7
High-Z
High-Z
High-Z
Data Outputs Low-Z
Data Inputs High-Z
L
L
L
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 2.5 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured ±200 mV from steady-state voltage.
Maximum Ratings
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
Storage Temperature
Output Short-Circuit Current
at V
CC
= 3.3 V and V
O
= 0 V
**
K-Type
A-Type
Symbol
V
CC
V
I
V
O
P
D
T
a
T
stg
| I
OS
|
Min.
-0.3
-0.5
-0.5
-
-40
-40
-65
Max.
4.6
V
CC
+ 0.5
V
CC
+ 0.5
1
85
125
150
100
Unit
V
V
V
W
°C
°C
mA
**
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
2
November 01, 2001
Preliminary
Recommended
Operating Conditions
Power Supply Voltage
Input Low Voltage
*
Symbol
V
CC
V
IL
V
IH
Conditions
Min.
3.0
-0.3
2.0
UL62H1708A
Max.
3.6
0.8
V
CC
+ 0.3
Unit
V
V
V
Input High Voltage
* -2 V at Pulse Width 10 ns
Electrical Characteristics
Supply Current - Operating Mode
Symbol
I
CC(OP)
V
CC
V
IL
V
IH
t
cW
t
cW
t
cW
V
CC
Conditions
=
=
=
=
=
=
3.6 V
0.8 V
2.0 V
35 ns
55 ns
70 ns
Min.
Max.
Unit
90
70
60
100
mA
mA
mA
µA
Supply Current - Standby Mode
(CMOS level)
Supply Current - Standby Mode
(TTL level)
I
CC(SB)
V
E1
= V
E2
= 3.6 V
= V
CC
- 0.2 V
= 3.6 V
= 2.0 V
I
CC(SB)1
V
CC
V
E1
= V
E2
K-Type
A-Type
Output High Voltage
Output Low Voltage
Input High Leakage Current
Input Low Leakage Current
Output High Current
Output Low Current
Output Leakage Current
High at Three-State Outputs
Low at Three-State Outputs
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
V
CC
I
OH
V
CC
I
OL
V
CC
V
IH
V
CC
V
IL
V
CC
V
OH
V
CC
V
OL
V
CC
V
OH
V
CC
V
OL
= 3.0 V
= -0.5 mA
= 3.0 V
= 0.5 mA
= 3.6 V
= 3.6 V
= 3.6 V
= 0V
=
=
=
=
3.0 V
2.0 V
3.0 V
0.4 V
2.2
10
20
mA
mA
V
0.4
2
-2
-0.5
0.5
V
µA
µA
mA
mA
I
OHZ
I
OLZ
= 3.6 V
= 3.6 V
= 3.6 V
= 0V
2
-2
µA
µA
November 01, 2001
3
UL62H1708A
Symbol
Alt.
t
RC
t
AA
t
ACE
t
OE
t
HZCE
t
HZOE
t
LZCE
t
LZOE
t
OH
t
PU
t
PD
IEC
t
cR
t
a(A)
t
a(E)
t
a(G)
t
dis(E)
t
dis(G)
t
en(E)
t
en(G)
t
v(A)
3
0
3
0
35
Min.
Preliminary
35
Max.
Min.
Switching Characteristics
Read Cycle
Read Cycle Time
Address Access Time to Data Valid
Chip Enable Access Time to Data Valid
G LOW to Data Valid
E1 HIGH or E2 LOW to Output in High-Z
G HIGH to Output in High-Z
E1 LOW or E2 HIGH to Output in Low-Z
G LOW to Output in Low-Z
Output Hold Time from Address Change
E1 LOW or E2 HIGH to Power-Up Time
E1 HIGH or E2 LOW to Power-Down Time
55
Unit
Max.
35
35
35
15
12
12
55
55
55
25
15
15
3
0
3
0
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
Write Cycle
Write Cycle Time
Write Pulse Width
Write Setup Time
Address Setup Time
Address Valid to End of Write
Chip Enable Setup Time
Pulse Width Chip Enable to End of Write
Data Setup Time
Data Hold Time
Address Hold from End of Write
W LOW to Output in High-Z
G HIGH to Output in High-Z
W HIGH to Output in Low-Z
G LOW to Output in Low-Z
Symbol
Alt.
t
WC
t
WP
t
WP
t
AS
t
AW
t
CW
t
CW
t
DS
t
DH
t
AH
t
HZWE
t
HZOE
t
LZWE
t
LZOE
IEC
t
cW
t
w(W)
t
su(W)
t
su(A)
t
su(A-WH)
Min.
35
Max.
Min.
55
Unit
Max.
35
20
20
0
20
25
25
15
0
0
15
12
0
0
55
35
35
0
40
40
40
25
0
0
20
15
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
su(E)
t
w(E)
t
su(D)
t
h(D)
t
h(A)
t
dis(W)
t
dis(G)
t
en(W)
t
en(G)
4
November 01, 2001
Preliminary
Data Retention Mode
Data Retention
Characteristics
Data Retention Supply Voltage
Data Retention Supply Current
Data Retention Setup Time
Operating Recovery Time
t
CDR
t
R
Symbol
Conditions
Alt.
IEC
V
CC(DR)
I
CC(DR)
t
su(DR)
t
rec
V
CC(DR)
= 2 V
V
E1
=V
E2
= V
CC(DR)
- 0.2 V
UL62H1708A
Min.
1.5
Typ.
Max.
3.6
30
Unit
V
µA
ns
ns
See Data Retention
Waveforms (below)
0
t
cR
Data Retention Mode E1 - controlled
V
CC
3.0 V
V
CC(DR)
≥
1.5 V
2.0 V
0V
t
su(DR)
Data Retention
t
rec
2.0 V
E1
V
E2(DR)
≥
V
CC(DR)
- 0.2 V or V
E2(DR)
≤
0.2 V
V
CC(DR)
- 0.2 V
≤
V
E1(DR)
≤
V
CC(DR)
+ 0.2 V
Data Retention Mode E2 - controlled
3.0 V
V
CC(DR)
≥
1.5 V
t
DR
0.8 V
0V
Data Retention
t
rec
0.8 V
V
CC
E2
V
E1(DR)
≥
V
CC(DR)
- 0.2 V or V
E1(DR)
≤
0.2 V
V
E2(DR)
≤
0.2 V
November 01, 2001
5
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