DS1225Y
DS1225Y
64K Nonvolatile SRAM
FEATURES
PIN ASSIGNMENT
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
•
10 years minimum data retention in the absence of
external power
•
Data is automatically protected during power loss
•
Directly replaces 8K x 8 volatile static RAM or EE-
PROM
•
Unlimited write cycles
•
Low-power CMOS
•
JEDEC standard 28–pin DIP package
•
Read and write access times as fast as 150 ns
•
Full
±10%
operating range
•
Optional
industrial temperature range of –40°C to
+85°C, designated IND
28–PIN ENCAPSULATED PACKAGE
720 MIL EXTENDED
PIN DESCRIPTION
A0–A12
DQ0–DQ7
CE
WE
OE
V
CC
GND
NC
–
–
–
–
–
–
–
–
Address Inputs
Data In/Data Out
Chip Enable
Write Enable
Output Enable
Power (+5V)
Ground
No Connect
DESCRIPTION
The DS1225Y 64K Nonvolatile SRAM is a 65,536–bit,
fully static, nonvolatile RAM organized as 8192 words
by 8 bits. Each NV SRAM has a self–contained lithium
energy source and control circuitry which constantly
monitors V
CC
for an out–of–tolerance condition. When
such a condition occurs, the lithium energy source is
automatically switched on and write protection is uncon-
ditionally enabled to prevent data corruption. The NV
SRAM can be used in place of existing 8K x 8 SRAMs
directly conforming to the popular bytewide 28–pin DIP
standard. The DS1225Y also matches the pinout of the
2764 EPROM or the 2864 EEPROM, allowing direct
substitution while enhancing performance. There is no
limit on the number of write cycles that can be executed
and no additional support circuitry is required for micro-
processor interfacing.
021998 1/8
DS1225Y
READ MODE
The DS1225Y executes a read cycle whenever WE
(Write Enable) is inactive (high) and CE (Chip Enable)
and OE (Output Enable) are active (low). The unique
address specified by the 13 address inputs (A
0
–A
12
) de-
fines which of the 8192 bytes of data is to be accessed.
Valid data will be available to the eight data output driv-
ers within t
ACC
(Access Time) after the last address in-
put signal is stable, providing that CE and OE access
times are also satisfied. If CE and OE access times are
not satisfied, then data access must be measured from
the later occurring signal and the limiting parameter is
either t
CO
for CE or t
OE
for OE rather than address ac-
cess.
recovery time (t
WR
) before another cycle can be initi-
ated. The OE control signal should be kept inactive
(high) during write cycles to avoid bus contention. How-
ever, if the output drivers are enabled (CE and OE ac-
tive) then WE will disable the outputs in t
ODW
from its
falling edge.
DATA RETENTION MODE
The DS1225Y provides full functional capability for V
CC
greater than 4.5 volts and write protects at 4.25 nominal.
Data is maintained in the absence of V
CC
without any
additional support circuitry. The DS1225Y constantly
monitors V
CC
. Should the supply voltage decay, the NV
SRAM automatically write protects itself, all inputs be-
come “don’t care,” and all outputs become high imped-
ance. As V
CC
falls below approximately 3.0 volts, a
power switching circuit connects the lithium energy
source to RAM to retain data. During power–up, when
V
CC
rises above approximately 3.0 volts, the power
switching circuit connects external V
CC
to RAM and dis-
connects the lithium energy source. Normal RAM oper-
ation can resume after V
CC
exceeds 4.5 volts.
WRITE MODE
The DS1225Y executes a write cycle whenever the WE
and CE signals are active (low) after address inputs are
stable. The latter occurring falling edge of CE or WE will
determine the start of the write cycle. The write cycle is
terminated by the earlier rising edge of CE or WE. All
address inputs must be kept valid throughout the write
cycle. WE must return to the high state for a minimum
021998 2/8
DS1225Y
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
–0.3V to +7.0V
0°C to 70°C; –40°C to +85°C for IND parts
–40°C to +70°C; –40°C to +85°C for IND parts
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Power Supply Voltage
Input Logic 1
Input Logic 0
SYM
V
CC
V
IH
V
IL
MIN
4.5
2.2
0.0
TYP
5.0
MAX
5.5
V
CC
+0.8
(t
A
: See Note 10)
UNITS
V
V
V
NOTES
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Input Leakage Current
I/O Leakage Current
CE > V
IH
< V
CC
Output Current @ 2.4V
Output Current @ 0.4V
Standby Current CE = 2.2V
Standby Current CE = V
CC
–0.5V
Operating Current t
CYC
=200 ns
(Commercial)
Operating Current t
CYC
=200 ns
(Industrial)
Write Protection Voltage
SYMBOL
I
IL
I
IO
I
OH
I
OL
I
CCS1
I
CCS2
I
CCO1
I
CCO1
V
TP
4.25
MIN
–1.0
–1.0
–1.0
2.0
5
3
TYP
(t
A
: See Note 10; V
CC
= 5V
±
10%)
MAX
+1.0
+1.0
UNITS
µA
µA
mA
mA
10
5
75
85
mA
mA
mA
mA
V
10
NOTES
021998 3/8
DS1225Y
AC ELECTRICAL CHARACTERISTICS
DS1225Y-150
PARAMETER
Read Cycle Time
Access Time
OE to Output Valid
CE to Output Valid
OE or CE to
Output Active
Output High Z from De-
selection
Output Hold from Ad-
dress Change
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
Output High Z from WE
Output Active from WE
Data Setup Time
Data Hold Time
SYMBOL
t
RC
t
ACC
t
OE
t
CO
t
COE
t
OD
t
OH
t
WC
t
WP
t
AW
t
WR1
t
WR2
t
ODW
t
OEW
t
DS
t
DH1
t
DH2
5
60
0
10
5
150
100
0
0
10
35
5
70
0
10
5
35
5
170
120
0
0
10
35
MIN
150
150
70
150
5
35
MAX
MIN
170
(t
A
: See Note 10; V
CC
=5.0V
±
10%)
DS1225Y-170
MAX
DS1225Y-200
MIN
200
170
80
170
5
35
5
200
150
0
0
10
35
5
80
0
10
200
100
200
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
13
5
5
4
12
13
3
5
5
NOTES
CAPACITANCE
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN
TYP
MAX
10
10
UNITS
pF
pF
(t
A
= 25
°
C)
NOTES
021998 4/8
DS1225Y
READ CYCLE
ADDRESSES
V
IH
V
IL
t
ACC
V
IH
CE
V
IH
OE
V
IL
t
OE
V
IL
t
COE
t
COE
t
CO
t
RC
V
IH
V
IL
V
IH
V
IH
V
IL
t
OH
V
IH
t
OD
SEE NOTE 1
D
OUT
t
OD
V
OH
OUTPUT
V
OH
V
OL
DATA VALID V
OL
WRITE CYCLE 1
ADDRESSES
V
IH
V
IL
t
AW
CE
t
WC
V
IH
V
IL
V
IH
V
IL
V
IL
t
WP
V
IL
t
WR1
V
IL
V
IH
t
OEW
WE
V
IH
t
ODW
V
IL
HIGH
IMPEDANCE
t
DS
V
IH
D
OUT
t
DH1
V
IH
DATA IN
STABLE
V
IL
V
IL
D
IN
SEE NOTE 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
ADDRESSES
V
IH
V
IL
t
AW
t
WC
V
IH
V
IL
t
WR2
t
WP
V
IH
V
IL
V
IL
V
IL
V
IH
V
IH
WE
t
COE
D
OUT
V
IH
D
IN
DATA IN
STABLE
V
IL
V
IL
V
IL
V
IL
V
IH
V
IL
CE
t
ODW
t
DS
t
DH2
V
IH
SEE NOTE 2, 3, 4, 6, 7, 8 AND 13
021998 5/8
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