CXD3511AQ
Digital Signal Driver/Timing Generator
Description
The CXD3511AQ incorporates digital signal
processor type RGB driver, color shading correction,
selectable delay line and timing generator functions
onto a single IC. Operation is possible with a system
clock up to 200 [MHz] (max.). This IC can process
video signals in bands up to UXGA standard, and
can output the timing signals for driving various Sony
LCD panels such as UXGA, SXGA and XGA.
Features
•
Various picture quality adjustment functions such
as user adjustment, white balance adjustment and
gamma correction
•
OSD MIX, black frame processing, mute and
limiter functions
•
LCD panel color shading correction function
•
Selectable delay line
•
Drives various Sony data projector LCD panels
such as UXGA, SXGA and XGA
•
Controls the CXA3562AR and CXA7000R sample-
and-hold drivers
•
Line inversion and field inversion signal generation
•
Supports AC drive of LCD panels during no signal
Applications
LCD projectors and other video equipment
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
(V
SS
= 0V)
•
Supply voltage
•
Input voltage
V
DD1
V
SS
– 0.5 to +3.0
V
V
DD2
V
SS
– 0.5 to +4.0
V
V
I
V
SS
– 0.5 to V
DD1
+ 0.5 V
240 pin QFP (Plastic)
•
Output voltage
V
O
V
SS
– 0.5 to V
DD1
+ 0.5 V
•
Storage temperature
Tstg
–55 to +125
°C
•
Junction temperature
Tj
125
°C
Recommended Operating Conditions
2.3 to 2.7
•
Supply voltage
V
DD1
V
DD2
3.0 to 3.6
•
Operating temperature
Topr
–20 to +75
V
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02401-PS
CXD3511AQ
Block Diagram
R, G, B IN
R, G, B OSD
YM
YS
8
×
2
×
3
2
×
2
×
3
2
2
DSD
10
×
2
×
3
R, G, B OUT
PCTL
PCLK
PDAT
10
CLKOUT
PARALLEL I/F
PLL
TG
CTRL
RGT, DWN
PCG, BLK, HST,
ENBR, ENBL, VSTR,
VSTL, VCKR, VCKL,
HCK1, DCK1, DCK2,
HCK2, DCK1X, DCK2X,
XRGT, FRP, XFRP,
PRG, DENB, CLP,
PO1, PO2, PO3, PO4,
PO5, PST, HD1, HD2
CLKC
CLKP
CLKN
CLKSEL1
CLKSEL2
PLLDIV
HDIN
VDIN
D Q
Q
Direct Clear
XCLR1
XCLR2
XCLR3
–2–
CXD3511AQ
Pin Configuration
R2OUT9
180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
R1IN2 181
R1IN1 182
R1IN0 183
R2IN7 184
R2IN6 185
V
DD2
186
V
SS
187
R2IN5 188
R2IN4 189
R2IN3 190
R2IN2 191
R2IN1 192
R2IN0 193
G1IN7 194
G1IN6 195
G1IN5 196
V
DD1
197
V
SS
198
G1IN4 199
G1IN3 200
G1IN2 201
G1IN1 202
G1IN0 203
G2IN7 204
G2IN6 205
G2IN5 206
G2IN4 207
G2IN3 208
V
DD1
209
V
SS
210
G2IN2 211
G2IN1 212
G2IN0 213
B1IN7 214
B1IN6 215
B1IN5 216
B1IN4 217
B1IN3 218
B1IN2 219
B1IN1 220
V
DD1
221
V
SS
222
B1IN0 223
B2IN7 224
B2IN6 225
B2IN5 226
B2IN4 227
B2IN3 228
B2IN2 229
B2IN1 230
B2IN0 231
R1OSD1 232
R1OSD0 233
V
DD2
234
V
SS
235
G1OSD1 236
G1OSD0 237
B1OSD1 238
B1OSD0 239
YM1 240
R1OUT8
DCK1X
DCK2X
TEST6
TEST5
TEST4
TEST3
TEST2
TEST1
R1IN3
R1IN4
R1IN5
R1IN6
R1IN7
XRGT
DENB
ENBR
VCKR
XFRP
HCK2
HCK1
DCK1
DCK2
VSTR
SHST
VCKL
ENBL
CTRL
VSTL
DWN
V
DD2
V
DD1
V
DD1
V
DD1
V
DD2
V
DD2
V
DD2
PRG
PCG
RGT
PO5
PO4
PO1
PO2
PO3
HD1
FRP
HD2
HST
CLP
PST
BLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
120 R1OUT7
119 R1OUT6
118 R1OUT5
117 R1OUT4
116 R1OUT3
115 V
SS
114 V
DD2
113 R1OUT2
112 R1OUT1
111 R1OUT0
110 R2OUT9
109 R2OUT8
108 R2OUT7
107 R2OUT6
106 R2OUT5
105 R2OUT4
104 R2OUT3
103 R2OUT2
102 V
SS
101 V
DD1
100 V
DD2
99 R2OUT1
98 R2OUT0
97 G1OUT9
96 G1OUT8
95 G1OUT7
94 G1OUT6
93 G1OUT5
92 G1OUT4
91 G1OUT3
90 V
SS
89 V
DD1
88 G1OUT2
87 G1OUT1
86 G1OUT0
85 G2OUT9
84 V
DD2
83 G2OUT8
82 G2OUT7
81 G2OUT6
80 G2OUT5
79 G2OUT4
78 V
SS
77 V
DD1
76 G2OUT3
75 G2OUT2
74 G2OUT1
73 G2OUT0
72 B1OUT9
71 B1OUT8
70 B1OUT7
69 B1OUT6
68 B1OUT5
67 V
SS
66 V
DD2
65 B1OUT4
64 B1OUT3
63 B1OUT2
62 B1OUT1
61 B1OUT0
1
YS1
2
R2OSD1
3
R2OSD0
4
G2OSD1
5
G2OSD0
6
V
DD2
7
V
SS
8
B2OSD1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
V
DD2
V
DD1
V
DD1
V
DD1
V
DD2
V
DD1
V
DD2
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
HDIN
VDIN
CLKSEL1
CLKSEL2
CLKOUT
B2OUT0
B2OUT1
B2OUT2
B2OUT3
B2OUT4
V
SS
B2OUT5
B2OUT6
B2OUT7
B2OUT8
B2OSD0
B2OUT9
YM2
YS2
PCTL
PCLK
PDAT9
PDAT8
PDAT7
PDAT6
PLLDIV
PDAT5
PDAT4
PDAT3
PDAT2
PDAT1
PDAT0
XCLR1
XCLR2
XCLR3
CLKC
CLKP
CLKN
–3–
CXD3511AQ
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Symbol
YS1
R2OSD1
R2OSD0
G2OSD1
G2OSD0
V
DD2
V
SS
B2OSD1
B2OSD0
YM2
YS2
PCTL
PCLK
PDAT9
PDAT8
PDAT7
PDAT6
V
DD2
V
SS
PDAT5
PDAT4
PDAT3
PDAT2
PDAT1
V
DD1
PDAT0
XCLR1
XCLR2
XCLR3
V
SS
HDIN
VDIN
V
SS
V
SS
CLKC
V
DD1
V
DD1
I/O
I
I
I
I
I
—
—
I
I
I
I
I
I
I
I
I
I
—
—
I
I
I
I
I
—
I
I
I
I
—
I
I
—
—
I
—
—
OSD YS input (port 1)
OSD Red data input (port 2)
OSD Red data input (port 2)
OSD Green data input (port 2)
OSD Green data input (port 2)
I/O power supply
GND
OSD Blue data input (port 2)
OSD Blue data input (port 2)
OSD YM input (port 2)
OSD YS input (port 2)
Parallel I/F control signal input
Parallel I/F clock input
Parallel I/F data input
Parallel I/F data input
Parallel I/F data input
Parallel I/F data input
I/O power supply
GND
Parallel I/F data input
Parallel I/F data input
Parallel I/F data input
Parallel I/F data input
Parallel I/F data input
Internal operation power supply
Parallel I/F data input
External clear (Low: reset)
External clear (Low: reset)
External clear (Low: reset)
GND
Horizontal sync signal input
Vertical sync signal input
GND
GND
Clock input (CMOS input)
Internal operation power supply
Internal operation power supply
–4–
—
—
—
—
—
—
—
—
H
H
H
—
—
—
—
—
—
—
—
Description
Input pin
processing for
open status
L
—
—
—
—
—
—
—
—
L
L
H
—
—
—
—
—
CXD3511AQ
Pin
No.
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Symbol
CLKP
CLKN
V
DD2
CLKSEL1
V
DD1
V
SS
CLKSEL2
PLLDIV
V
SS
CLKOUT
V
SS
B2OUT0
B2OUT1
B2OUT2
B2OUT3
B2OUT4
V
DD2
V
SS
B2OUT5
B2OUT6
B2OUT7
B2OUT8
B2OUT9
B1OUT0
B1OUT1
B1OUT2
B1OUT3
B1OUT4
V
DD2
V
SS
B1OUT5
B1OUT6
B1OUT7
B1OUT8
B1OUT9
G2OUT0
G2OUT1
I/O
I
I
—
I
—
—
I
I
—
O
—
O
O
O
O
O
—
—
O
O
O
O
O
O
O
O
O
O
—
—
O
O
O
O
O
O
O
Description
Clock input (small-amplitude differential input, positive polarity)
Clock input (small-amplitude differential input, negative polarity)
I/O power supply
Input clock selection. (High: CLKC, Low: CLKP CLKN)
,
Internal operation power supply
GND
Internal clock path selection.
(High: no frequency division, Low: frequency division)
Internal PLL setting. (High: 55MHz or less, Low: 55MHz or more)
GND
Internal clock output (inverted output)
GND
Blue data output (port 2)
Blue data output (port 2)
Blue data output (port 2)
Blue data output (port 2)
Blue data output (port 2)
I/O power supply
GND
Blue data output (port 2)
Blue data output (port 2)
Blue data output (port 2)
Blue data output (port 2)
Blue data output (port 2)
Blue data output (port 1)
Blue data output (port 1)
Blue data output (port 1)
Blue data output (port 1)
Blue data output (port 1)
I/O power supply
GND
Blue data output (port 1)
Blue data output (port 1)
Blue data output (port 1)
Blue data output (port 1)
Blue data output (port 1)
Green data output (port 2)
Green data output (port 2)
–5–
Input pin
processing for
open status
—
—
—
L
—
—
L
L
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
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