SSM3J56MFV
TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type (U-MOSⅥ)
SSM3J56MFV
○
Load Switching Applications
•
•
1.2 V drive
Low ON-resistance: R
DS(ON)
= 390 mΩ (max) (@V
GS
= -4.5 V)
R
DS(ON)
= 480 mΩ (max) (@V
GS
= -2.5 V)
R
DS(ON)
= 660 mΩ (max) (@V
GS
= -1.8 V)
R
DS(ON)
= 900 mΩ (max) (@V
GS
= -1.5 V)
R
DS(ON)
= 4000 mΩ (max) (@V
GS
= -1.2 V)
Unit: mm
Absolute Maximum Ratings
(Ta = 25°C)
Characteristic
Drain-Source voltage
Gate-Source voltage
Drain current
DC
Pulse
Symbol
V
DSS
V
GSS
I
D
(Note 1)
I
DP
(Note 1)
P
D
(Note 2)
Power dissipation
Channel temperature
Storage temperature range
P
D
(Note 3)
t
<
5s
T
ch
T
stg
Rating
-20
±
8
-800
-1600
150
500
800
150
−55
to 150
°C
°C
mW
Unit
V
V
mA
1.Gate
2.Source
3.Drain
VESM
JEDEC
―
Note: Using continuously under heavy loads (e.g. the application of high
temperature/current/voltage and the significant change in temperature,
JEITA
―
etc.) may cause this product to decrease in the reliability significantly even
TOSHIBA
2-1L1B
if the operating conditions (i.e. operating temperature/current/voltage, etc.)
are within the absolute maximum ratings.
Weight: 1.5mg (typ.)
Please design the appropriate reliability upon reviewing the Toshiba
Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual
reliability data (i.e. reliability test report and estimated failure rate, etc).
Note 1: The channel temperature should not exceed 150°C during use.
Note 2: Mounted on a FR4 board.
(25.4 mm
×
25.4 mm
×
1.6 mm, Cu Pad: 0.585 mm
2
)
Note 3: Mounted on a FR4 board.
(25.4 mm
×
25.4 mm
×
1.6 mm, Cu Pad: 645 mm
2
)
Marking
3
Equivalent Circuit
(top view)
3
PW
1
2
1
2
Handling Precaution
When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is
protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that
come into direct contact with devices should be made of antistatic materials.
Thermal resistance R
th (ch-a)
and Power dissipation P
D
vary depending on board material, board area, board thickness
and pad area. When using this device, please take heat dissipation into consideration.
Start of commercial production
2011-05
1
2014-03-01
SSM3J56MFV
Electrical Characteristics
(Ta = 25°C)
Characteristic
Drain-source breakdown voltage
Drain cut-off current
Gate leakage current
Gate threshold voltage
Forward transfer admittance
Symbol
Test Conditions
Min
-20
.(Note
5)
-15
⎯
⎯
-0.3
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
0.5
⎯
⎯
⎯
⎯
⎯
⎯
V
DS
= -10 V, V
GS
= 0 V, f = 1 MHz
V
DD
= -10 V, I
D
= -200 mA
V
GS
= 0 to -2.5 V, R
G
= 50
Ω
V
DD
= -10 V, I
D
= -800 mA,
V
GS
= -4.5 V
I
D
= 800 mA, V
GS
= 0 V
(Note 4)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Typ.
⎯
⎯
⎯
⎯
⎯
1.0
310
380
470
560
770
100
16
10
8
26
1.6
0.2
0.4
0.9
Max
⎯
⎯
-1
±1
-1.0
⎯
390
480
660
900
4000
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
1.2
V
nC
ns
pF
mΩ
Unit
V
V
μA
μA
V
S
V
(BR) DSS
I
D
= -1 mA, V
GS
= 0 V
V
(BR) DSX
I
D
= -1 mA, V
GS
= 5 V
I
DSS
I
GSS
V
th
⏐Y
fs
⏐
V
DS
= -20 V, V
GS
= 0 V
V
GS
=
±8
V, V
DS
= 0 V
V
DS
= -3 V, I
D
= -1 mA
V
DS
= -3 V, I
D
= -100 mA
I
D
= -800 mA, V
GS
= -4.5 V
I
D
= -500 mA, V
GS
= -2.5 V
Drain–source ON-resistance
R
DS (ON)
I
D
= -200 mA, V
GS
= -1.8 V
I
D
= -100 mA, V
GS
= -1.5 V
I
D
= -10 mA, V
GS
= -1.2 V
Input capacitance
Output capacitance
Reverse transfer capacitance
Switching time
Total gate charge
Gate-source charge
Gate-drain charge
Drain-source forward voltage
Turn-on time
Turn-off time
C
iss
C
oss
C
rss
t
on
t
off
Q
g
Q
gs1
Q
gd
V
DSF
Note 4: Pulse test
Note 5: If a forward bias is applied between gate and source, this device enters V(BR)DSX mode.
Note that the drain-source breakdown voltage is lowered in this mode.
Switching Time Test Circuit
(a) Test Circuit
0
OUT
IN
−2.5
V
R
G
R
L
V
DD
10%
(b) V
IN
0V
90%
−
2.5V
10
μs
(c) V
OUT
V
DS (ON)
90%
10%
t
r
t
on
t
off
t
f
V
DD
= -10 V
R
G
=
50
Ω
Duty
≤
1%
V
IN
: t
r
, t
f
<
5 ns
Common Source
Ta
=
25°C
V
DD
Notice on Usage
V
th
can be expressed as the voltage between gate and source when the low operating current value is I
D
= -1 mA for
this product. For normal switching operation, V
GS (on)
requires a higher voltage than V
th
and V
GS (off)
requires a lower
voltage than V
th.
(The relationship can be established as follows: V
GS (off)
< V
th
< V
GS (on).
)
Take this into consideration when using the device.
2
2014-03-01
SSM3J56MFV
I
D
– V
DS
-2.0
-4.5 V
-2.5 V
-10
-1.8 V
-1.5 V
I
D
– V
GS
(A)
I
D
I
D
-1.0
(A)
Drain current
-1.5
-1
Drain current
-0.1
Ta = 100 °C
-0.01
25 °C
-25 °C
-0.001
Common Source
VDS = -3 V
Pulse test
-1.0
-2.0
VGS = -1.2 V
-0.5
Common Source
Ta = 25 °C
Pulse test
0
-0.5
-1.0
-1.5
0
-0.0001
0
Drain–source voltage
V
DS
(V)
Gate–source voltage
V
GS
(V)
R
DS (ON)
– V
GS
1.6
ID = -10 mA
Common Source
Pulse test
1.6
R
DS (ON)
– V
GS
ID = -800 mA
Common Source
Pulse test
Drain–source ON-resistance
R
DS (ON)
(Ω)
Drain–source ON-resistance
R
DS (ON)
(Ω)
1.2
1.2
0.8
25 °C
0.4
Ta = 100 °C
0.8
25 °C
0.4
Ta = 100 °C
-25 °C
0
0
-2
-4
-6
-8
0
0
-2
-4
-6
-25 °C
-8
Gate–source voltage
V
GS
(V)
Gate–source voltage
V
GS
(V)
R
DS (ON)
– Ta
1.6
Common Source
Pulse test
1.6
R
DS (ON)
– I
D
Drain–source ON-resistance
R
DS (ON)
(Ω)
Drain–source ON-resistance
R
DS (ON)
(Ω)
-1.2 V
12
-1.5 V
1.2
-200 mA / -1.8 V
-100 mA / -1.5 V
0.8
-10 mA / -1.2 V
0.8
-1.8 V
0.4
ID = -800 mA / VGS = -4.5 V
-500 mA / -2.5 V
0
−50
0
50
100
150
0.4
VGS = -4.5 V
0
0
-2.5 V
Common Source
Ta = 25 °C
Pulse test
-1.5
-2.0
-0.5
-1.0
Ambient temperature
Ta
(°C)
Drain current
I
D
(A)
3
2014-03-01
Microchip MCU
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