= 12 V, VREG50/AVDD = 5 V (internal), VREG18/DVDD = 1.8 V (external), R
L
= 8 Ω + 33 μH, BCLK = 3.072 MHz and FSYNC =
48 kHz, T
A
= −40°C to +85°C, unless otherwise noted. The measurements are with a 20 kHz AES17 low-pass filter. The other load
impedances used are 4 Ω + 15 μH and 3 Ω +10 μH. Measurements are with a 20 kHz AES17 low-pass filter, unless otherwise noted.
The sine wave output powers above 20 W in 4 Ω cannot be continuous and may invoke the thermal limit indicator based on the power
dissipation capability of the board.
Table 1.
Parameter
DEVICE CHARACTERISTICS
Output Power/Channel
R
L
= 8 Ω
Symbol
P
OUT
Test Conditions/Comments
f = 1 kHz
THD + N = 1%, PV
DD
= 17 V
THD + N = 1%, PV
DD
= 12 V
THD + N = 1%, PV
DD
= 7 V
THD + N = 1%, PV
DD
= 5 V
THD + N = 10%, PV
DD
= 17 V
THD + N = 10%, PV
DD
= 12 V
THD + N = 10%, PV
DD
= 7 V
THD + N = 10%, PV
DD
= 5 V
THD + N = 1%, PV
DD
= 17 V
THD + N = 1%, PV
DD
= 12 V
THD + N = 1%, PV
DD
= 7 V
THD + N = 1%, PV
DD
= 5 V
THD + N = 10%, PV
DD
= 17 V
THD + N = 10%, PV
DD
= 12 V
THD + N = 10%, PV
DD
= 7 V
THD + N = 10%, PV
DD
= 5 V
P
OUT
= 9 W, R
L
= 8 Ω, PV
DD
= 12 V
P
OUT
= 9 W, R
L
= 8 Ω, PV
DD
= 12 V (low EMI mode)
P
OUT
= 30 W, R
L
= 4 Ω, PV
DD
= 17 V
P
OUT
= 30 W, R
L
= 4 Ω, PV
DD
= 17 V (low EMI mode)
P
OUT
= 5 W into R
L
= 8 Ω, f = 1 kHz, PV
DD
= 16 V
3
5
R
ON
I
OC
f
SW
V
OOS
Gain = 12.6 V
5.8
300
±1
±5.0
Min
Typ
Max
Unit
R
L
= 4 Ω
Efficiency
η
Total Harmonic
Distortion + Noise
Load Resistance
Load Inductance
Output FET On Resistance
Overcurrent Protection
Trip Point
Average Switching
Frequency
Differential Output DC
Offset Voltage
POWER SUPPLIES
Supply Voltage Range
THD + N
16
8.4
2.8
1.4
19.7
10.5
3.5
1.8
31.3
15.8
5.4
2.8
39.3
19.7
6.7
3.4
93.3
93.2
88
87.8
0.004
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
%
%
%
%
%
Ω
μH
mΩ
A peak
kHz
mV
10
110
AC Power Supply
Rejection Ratio
GAIN CONTROL
Output Voltage Peak
PV
DD
VREG50/AVDD
VREG18/DVDD
PSRR
AC
Guaranteed from PSRR test
Internal
Internal or external
V
RIPPLE
= 1 V rms at 1 kHz
Measured with 0 dBFS input at 1 kHz
Analog gain setting = 8.4 V/V with PV
DD
= 17 V
Analog gain setting = 12.6 V/V with PV
DD
= 17 V
Analog gain setting = 14.0 V/V with PV
DD
= 17 V
Analog gain setting = 15.0 V/V with PV
DD
= 17 V
Rev. 0| Page 3 of 41
4.5
4.5
1.62
5.0
1.80
87
17
5.5
1.98
73
V
V
V
dB
8.4
12.6
14
15
V peak
V peak
V peak
V peak
SSM3515
Parameter
SHUTDOWN CONTROL
1
Turn On Time, Volume
Ramp Disabled
f
S
= 12 kHz
f
S
= 24 kHz
f
S
= 48 kHz
f
S
= 96 kHz
f
S
= 192 kHz
Turn On Time, Volume
Ramp Enabled
f
S
= 12 kHz
f
S
= 24 kHz
f
S
= 48 kHz
f
S
= 96 kHz
f
S
= 192 kHz
Turn Off Time, Volume
Ramp Disabled
Turn Off Time, Volume
Ramp Enabled
f
S
= 12 kHz
f
S
= 24 kHz
f
S
= 48 kHz
f
S
= 96 kHz
f
S
= 192 kHz
Output Impedance
NOISE PERFORMANCE
2
Output Voltage Noise
Signal-to-Noise Ratio
PVDD ADC PERFORMANCE
PVDD Sense Full-Scale
Range
PVDD Sense Absolute
Accuracy
Resolution
DIE TEMPERATURE
Overtemperature
Warning
Overtemperature
Protection
1
2
Data Sheet
Symbol
t
WU
Test Conditions/Comments
Time from SPWDN = 0 to output switching,
DAC_HV = 1 or DAC_MUTE = 1, t
WU
= 4 FSYNC
cycles to 7 FSYNC cycles + 7.68 ms
8.01
7.84
7.76
7.72
7.70
t
WUR
Time from SPWDN = 0 to full volume output
switching, DAC_HV = 0 and DAC_MUTE = 0,
VOL = 0x40
t
WUR
= t
WU
+ 15.83 ms
t
WUR
= t
WU
+ 15.83 ms
t
WUR
= t
WU
+ 15.83 ms
t
WUR
= t
WU
+ 7.92 ms
t
WUR
= t
WU
+ 0.99 ms
Time from SPWDN = 1 to full power-down,
DAC_HV = 1 or DAC_MUTE = 1
Time from SPWDN = 1 to full power-down,
DAC_HV = 0 and DAC_MUTE = 0, VOL = 0x40
t
SDR
= t
SD
+ 15.83 ms
t
SDR
= t
SD
+ 15.83 ms
t
SDR
= t
SD
+ 15.83 ms
t
SDR
= t
SD
+ 7.92 ms
t
SDR
= t
SD
+ 0.99 ms
8.27
7.98
7.83
7.76
7.72
ms
ms
ms
ms
ms
Min
Typ
Max
Unit
23.84
23.67
23.59
15.64
8.69
100
24.10
23.81
23.66
15.68
8.71
t
SD
t
SDR
ms
ms
ms
ms
ms
µs
15.932
15.932
15.932
8.016
1.09
100
Z
OUT
e
n
SNR
f = 20 Hz to 20 kHz, A-weighted, PV
DD
= 12 V
f = 20 Hz to 20 kHz, A-weighted, PV
DD
= 17 V
P
OUT
= 8.2 W, R
L
= 8 Ω, A-weighted, PV
DD
= 12 V
P
OUT
= 31 W, R
L
= 4 Ω, A-weighted, PV
DD
= 17 V
PVDD with full-scale ADC out
PV
DD
= 15 V
PV
DD
= 5 V
Unsigned 8-bit output with 3.8 V offset
ms
ms
ms
ms
ms
kΩ
µV rms
µV rms
dB
dB
16.2
+8
+6
V
LSB
LSB
Bits
°C
°C
37.5
48
107
107
3.8
−8
−6
8
117
145
Guaranteed by design.
Noise performance is based on the bench data for T
A
= −40°C to +85°C.
Rev. 0| Page 4 of 41
Data Sheet
SSM3515
Software master power-down indicates that the clocks are turned off. Auto power-down indicates that there is no dither or zero input
signal with clocks on; the device enters soft power-down after 2048 cycles of zero input values. Quiescent indicates triangular dither with
zero input signal. All specifications are typical, with a 48 kHz sample rate, unless otherwise noted.
Table 2. Power Supply Current Consumption
1
Edge Rate
Control
Mode
Normal
No Load
REG_EN Pin
Low
Test Conditions
PV
DD
Software master
power-down
Auto power-down
Quiescent
Software master
power-down
Auto power-down
Quiescent
Software master
power-down
Auto power-down
Quiescent
Software master
power-down
Auto power-down
Quiescent
5V
0.01
0.01
4.10
0.01
310
4.64
0.01
0.01
4.00
0.01
310
4.60
I
PVDD
12 V
0.03
0.03
5.00
0.03
310
5.60
0.03
0.03
4.95
0.03
310
5.60
17 V
0.03
0.03
5.60
0.03
316
6.26
0.03
0.03
5.54
0.03
316
6.17
I
REG18
1.8 V
7
54
0.48
N/A
N/A
N/A
7
54
0.48
N/A
N/A
N/A
5V
0.01
0.01
4.10
0.01
310
4.74
0.01
0.01
4.70
0.01
310
4.60
4 Ω + 15 µH
I
PVDD
12 V
0.03
0.03
5.12
0.03
310
5.85
0.03
0.03
3.99
0.03
310
5.65
17 V
0.03
0.03
5.90
0.03
316
6.55
0.03
0.03
5.59
0.03
316
6.35
I
REG18
1.8 V
7
54
0.48
N/A
N/A
N/A
7
54
0.48
N/A
N/A
N/A
5V
0.01
0.01
4.10
0.01
310
4.74
0.01
0.01
4.02
0.01
310
4.60
8 Ω + 33 µH
I
PVDD
12 V
0.03
0.03
5.10
0.03
310
5.85
0.03
0.03
4.98
0.03
310
5.60
17 V
0.03
0.03
5.80
0.03
316
6.55
0.03
0.03
5.63
0.03
316
6.40
I
REG18
1.8 V
7
54
0.48
N/A
N/A
N/A
7
54
0.48
N/A
N/A
N/A
Unit
μA
μA
mA
μA
μA
mA
μA
μA
mA
μA
μA
mA
PVDD
Low EMI
Low
PVDD
1
N/A means not applicable.
Table 3. Power-Down Current
Parameter
POWER-DOWN CURRENT
Symbol
I
PVDD
Test Conditions/Comments
VREG18/DVDD = 1.8 V external, software master power-down, no BCLK/FSYNC
PV
DD
= 5 V
PV
DD
= 12 V
PV
DD
= 17 V
VREG18/DVDD = 1.8 V external
Min
27
30
30
Typ
38
39
39
7
Max
95
100
152
27
Unit
nA
nA
nA
μA
I
DVDD
Table 4. Digital Input/Output
Parameter
INPUT VOLTAGE
1
High (V
IH
)
BCLK, FSYNC, SCL, SDA
SDATA, ADDR
Low (V
IL
)
BCLK, FSYNC, SDATA, SCL, SDA
ADDR
INPUT LEAKAGE
High (I
IH
)
Low (I
IL
)
INPUT CAPACITANCE
OUTPUT VOLTAGE (SDATA)
High (V
OH
)
Low (V
OL
)
OUTPUT DRIVE STRENGTH
1
SDA
SDATA
BCLK Frequency (BCLK)
Sample Rate (FSYNC)
1
Min
Typ
Max
Unit
Test Comments/Comments
1.13
0.7 × VREG18/DVDD
−0.3
−0.3
5.5
1.98
+0.54
+1.98
1
1
5
V
V
V
V
µA
µA
pF
V
V
mA
mA
MHz
kHz
1.17
0.45
3
2
2.048
8
5
24
24.576
192
The pull-up resistor for SCL and SDA must be scaled according to the external pull-up voltage in the system. The typical value for a pull-up resistor for 1.8 V is 2.2 kΩ.
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