Ver. 1.2
6F, No. 100, Sec. 4, Civil Boulevard, Taipei, Taiwan
TEL: (02)8773-1100 FAX: 886-2-8773-2211
WWW : http://www.cmedia.com.tw
CMA8864-04
(3 DIMM)
FEATURES
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I
2
C, Mixed Voltage clock Synthesizer with Buffer
for PENTIUM
TM
& II CPU/PCI system (CK3D)
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Supports Pentium and Pentium II CPUs.
Two (2) copies of CPUCLK clock powered with
VDDL2, two (2) copies of CPUCLK powered
with VDD3..
Twelve (12) SDRAM clocks powered by VDD3.
Seven (7) copies of PCI clock (1/2 CPU clock or
asynchronous 2/5 CPU clock).
IOAPIC clock @14.318MHz driven by VDDL1.
24/48 MHz outputs (3.3V TTL)
Two Ref. Clock @ 14.318MHz (3.3V TTL).
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60mA buffer switching current @3.3V.
Optional common or mixed power supply mode
²
VDD1, 2, 3 = VDDL2, 1 = 3.3V
²
VDD1, 2, 3 = 3.3V; VDDL2, 1 = 2.5V
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< 250ps skew between CPU/SDRAM buffers.
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<500ps skew between PCI buffers.
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Power management controlled by CPU_STOP#,
PCI_STOP#.
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2
C Serial configuration interface.
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48 pins SSOP package.
PIN CONFIGURATIONS
VDD1
*REF0 / CPU3.3#_2.5
GND
XTAL_IN
XTAL_OUT
VDD2
*PCICLK_F / FS1
*PCICLK1 / FS2
GND
PCICLK2
PCICLK3
PCICLK4
PCICLK5
VDD2
PCICLK6 / PCI_STOP#
GND
SDRAM12
SDRAM11
VDD3
SDRAM10
SDRAM9
GND
SDATA
I
2
C
SDCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDL1
IOAPIC
REF1 / CPU_STOP#
GND
CPUCLK1
CPUCLK2
VDDL2
CPUCLK3
CPUCLK4
GND
SDRAM1
SDRAM2
VDD3
SDRAM3
SDRAM4
GND
SDRAM5
SDRAM6
VDD3
SDRAM7
SDRAM8
GND
48MHz / FS0*
24MHz / MODE*
2.5V / 3.3V
I/O PINS
*Internal pull-up
resistor 240
[
to 3.3V
£
on indicated pins.
POWER GROUPS
VDD1=REF, XTAL_IN, XTAL_OUT, PLL CORE
VDD3=SDRAM, 24/48MHz, CPUCLK3- 4
VDDL2=CPUCLK1-2
VDD2=PCICLK
VDDL1=IOAPIC
CMEI
1
CMA8864-04
Ver. 1.2
6F, No. 100, Sec. 4, Civil Boulevard, Taipei, Taiwan
TEL: (02)8773-1100 FAX: 886-2-8773-2211
WWW : http://www.cmedia.com.tw
PIN DESCRIPTION
NAME
VDD1
REF0
/ CPU3.3#_2.5
GND
XTAL_IN
XTAL_OUT
VDD2
PCICLK_F
/ FS1
PCICLK1
/ FS2
PCICLK2-5
PCICLK6
/ PCI_STOP#
SDRAM12-1
TYPE
P
I/O
G
I
O
P
I/O
I/O
O
I/O
O
NO.
1
2
3, 9, 16, 22,
27, 33, 39, 45
4
5
6, 14
7
8
10, 11, 12,
13
15
17, 18, 20,
21, 28, 29,
31, 32, 34,
35, 37, 38
19, 30, 36
20, 21, 28,
29, 31, 32,
34, 35,37, 38
23
24
25
DESCRIPTION
Analog 3.3V power supply for PLL core, REF, XTAL_IN/_OUT.
14.318MHz clock output.
/ Indicates VDDL2 power supply, 0=3.3V CPU, 1=2.5V CPU.
Ground.
Crystal input.
Crystal output.
3.3V I/O power supply for PCICLK.
PCI clock output free-running, TTL compatible 3.3V.
/ Frequency select pin, latched input, internal pull-High.
PCI clock output TTL compatible 3.3V.
/ Frequency select pin, latched input, internal pull-High.
PCI clock output TTL compatible 3.3V.
PCI clock output TTL compatible 3.3V.
/ halts PCICLK at logic 0 level when input low, MODE=0 (Mobil mode)
SDRAM clock output.
VDD3
SDRAM10:1
P
O
3.3V I/O power supply for SDRAM, 24/48MHz.
SDRAM clock outputs powered by VDD3.
Data input pin for I
2
C bus.
Clock input pin for I
2
C bus.
24MHz clock output 3.3V.
MODE=1
Pin 15 = PCICLK6
Pin 46 = REF1
MODE=0
Pin 15 = CPI_STOP#
Pin 46 = CPU_STOP#
48MHz clock output 3.3V.
/ Frequency select pin, latched input, internal pull-High.
CPU and Host clock output 3.3V output, powered by VDD3.
CPU and Host clock output 3.3V output, powered by VDD3.
2.5V/3.3V I/O power supply.
CPU and Host clock output 2.5V/3.3V output, powered by VDDL2.
CPU and Host clock output 2.5V/3.3V output, powered by VDDL2.
14.318MHz clock output.
/ halts CPUCLK at logic 0 level when input low, MODE=0 (Mobil mode)
14.318MHz clock output 2.5V/3.3V, powered by VDDL1.
2.5V/3.3V I/O power supply.
SDATA
SDCLK
24MHz
/ MODE
48MHz
/ FS0
CPUCLK4
CPUCLK3
VDDL2
CPUCLK2
CPUCLK1
REF1
/ CPU_STOP#
IOAPIC
VDDL1
I
I
I/O
I/O
O
O
P
O
O
I/O
I/O
P
26
40
41
42
43
44
46
47
48
CMEI
2
CMA8864-04
Ver. 1.2
6F, No. 100, Sec. 4, Civil Boulevard, Taipei, Taiwan
TEL: (02)8773-1100 FAX: 886-2-8773-2211
WWW : http://www.cmedia.com.tw
CPU CLOCK FREQUENCY TABLE (in MHz)
SEL2 SEL1 SEL0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
CPU, SDRAM
66.8
60
75
83.3
68.5
83.3
75
50
PCI
33.4 (1/2 CPU)
30 (1/2 CPU)
37.5 (1/2 CPU)
33.3 (2/5 CPU)
34.25 (1/2 CPU)
41.65 (1/2 CPU)
30 (2/5 CPU)
25 (1/2 CPU)
I
2
C SERIAL CONTROL
I
2
C Specification
Address assignment
Transfer type
Transfer rate
Data byte format
Address format
General call
7 bit
Slaver / Receiver
100kbits/s (standard mode)
8 bits
A6 A5 A4 A3 A2 A1
1
1
0
1
0
0
No respond
A0 R/Ws +8 bits dummy
+8 bits dummy
1
0 Command Code Command Code
SERIAL CONTROL REGISTERS
A) The serial bits will be read in the following order :
Byte 0
-
Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1
-
Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N
-
Bits 7, 6, 5, 4, 3, 2, 1, 0
B)
The PIN# column lists the affected pin number where application. The values in the @Pup column gives the
state at true power up. Registers are set to the values shown only on the true power up.
CMEI
3
CMA8864-04
Ver. 1.2
6F, No. 100, Sec. 4, Civil Boulevard, Taipei, Taiwan
TEL: (02)8773-1100 FAX: 886-2-8773-2211
WWW : http://www.cmedia.com.tw
Byte 0 : Function and Frequency Select Register (1=enable, 0=disable)
Bit
7
PIN#
--
@Pup
0
Description
Must be 0 for normal operation.
0 --
¡ Ó
frequency modulation.
1.5%
1 --
¡ Ó
frequency modulation.
0
.5%
Bit6 Bit5 Bit4
CPU, SDRAM
PCI
33.4 (1/2 CPU)
66.8
1
1
1
30 (1/2 CPU)
60
0
1
1
37.5 (1/2 CPU)
75
1
0
1
33.3 (2/5 CPU)
83.3
0
0
1
34.5 (1/2 CPU)
68.5
1
1
0
41.65 (1/2 CPU)
83.3
0
1
0
30 (2/5 CPU)
75
1
0
0
25 (1/2 CPU)
50
0
0
0
0 -- Frequency is selected by hardware select, latched inputs.
1 -- Frequency is selected by Bit 6 : 4.
Must be 0 for normal operation.
0 -- Frequency modulation center spread type.
1 -- Frequency modulation down spread type.
0 -- Normal.
1 -- Frequency modulation enabled type.
0 -- Normal.
1 -- Tristate all outputs.
6
5
4
--
--
--
0
0
0
3
2
--
--
0
0
1
0
--
--
0
0
Byte 1 : CPU Active/Inactive Register (1=enable, 0=disable)
Bit
7
6
5
4
3
2
1
0
PIN#
26
25
--
--
40
41
43
44
@Pup
1
1
X
X
1
1
1
1
Description
48MHz (Active/Inactive)
24MHz (Active/Inactive)
Reserved
Reserved
CPUCLK4 (Active/Inactive)
CPUCLK3 (Active/Inactive)
CPUCLK2 (Active/Inactive)
CPUCLK1 (Active/Inactive)
Byte 2 : PCI Active/Inactive Register (1=enable, 0=disable)
Bit
7
6
5
4
3
2
1
0
PIN#
--
7
15
13
12
11
10
8
@Pup
X
1
1
1
1
1
1
1
Description
Reserved
PCICLK_F (Active/Inactive)
PCICLK6 (Active/Inactive)
PCICLK5 (Active/Inactive)
PCICLK4 (Active/Inactive)
PCICLK3 (Active/Inactive)
PCICLK2 (Active/Inactive)
PCICLK1 (Active/Inactive)
CMEI
4
CMA8864-04
Ver. 1.2
6F, No. 100, Sec. 4, Civil Boulevard, Taipei, Taiwan
TEL: (02)8773-1100 FAX: 886-2-8773-2211
WWW : http://www.cmedia.com.tw
Byte 3 : SDRAM Active/Inactive Register (1=enable, 0=disable)
Bit
7
6
5
4
3
2
1
0
PIN#
28
29
31
32
34
35
37
38
@Pup
1
1
1
1
1
1
1
1
Description
SDRAM8 (Active/Inactive)
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
Byte 4 : Additional SDRAM Active/Inactive Register (1=enable,
0=disable)
Bit
7
6
5
4
3
2
1
0
PIN#
--
--
--
--
17
18
20
21
@Pup
X
X
X
X
1
1
1
1
Description
Reserved
Reserved
Reserved
Reserved
SDRAM12 (Active/Inactive)
SDRAM11 (Active/Inactive)
SDRAM10 (Active/Inactive)
SDRAM9 (Active/Inactive)
Byte 5 : Peripheral Active/Inactive Register (1=enable, 0=disable)
Bit
7
6
5
4
3
2
1
0
PIN#
--
--
--
47
--
--
46
2
@Pup
X
X
X
1
X
X
1
1
Description
Reserved
Reserved
Reserved
IOAPIC (Active/Inactive)
Reserved
Reserved
REF1 (Active/Inactive)
REF0(Active/Inactive)
Byte 6 : Reserved Optional Register for Future Requirements
Bit
7
6
5
4
3
2
1
0
PIN#
--
--
--
--
--
--
--
--
@Pup
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CMEI
5
CMA8864-04
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