CM8563
1.5A L
INEAR
B
US
T
ERMINATION
R
EGULATOR
GENERAL DESCRIPTION
The CM8563 is a low cost linear regulator designed to provide
a desired output voltage or termination voltage for various
applications. The device contains a high-speed operational
amplifier to provide excellent response to load transients.
The CM8563 is capable of sourcing or sinking up to 1.5A, and
peaks up to 3A of current while regulating an output VOUT
voltage to meet the JEDEC SSTL-2 and SSTL-3
specification. .
The CM8563 also incorporates a VFB pin to provide superior
load regulation and a VREF output as a reference for the
chipset and DDR DIMMS.
The CM8563 provides low profile 8-pin SOIC package to save
system space.
FEATURES
Ideal for DDR-I and DDR-II
8-pin SOIC package
Source and sink up to 1.5A, no heat sink required
Integrated power MOSFETs
No external resistors required
Minimum external components
APPLICATIONS
Mother Board
PCI/AGP Graphics
DDR Termination Voltage (SSTL-2 & SSTL-3)
PIN CONFIGURATION
SOP-8 (S08)
Top View
1
2
3
4
PG
GND
VFB
VREF
VOUT
VIN
VCCA
VDDQ
8
7
6
5
TYPICAL APPLICATION
VREF = 1.25V
U1
CM8563
VREF
0.1uF
PG
PG
VDDQ = 2.5V
VCCA = 2.5V
VDDQ
VOUT
220uF
VOUT = 1.25V
VCCA
VFB
VIN
50uF
GND
2003/03/28
Champion Microelectronic Corporation
Page 1
CM8563
1.5A L
INEAR
B
US
T
ERMINATION
R
EGULATOR
PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
PG
GND
VFB
VREF
VDDQ
VCCA
VIN
VOUT
Symbol
Power Good
Ground
Feedback pin for regulating VOUT
Buffered reference Voltage
Input for internal reference equal to VDDQ/2
Analog input
Power input
Output voltage for connection to termination resistors
Description
ORDERING INFORMATION
Part Number
CM8563IS
CM8563PIS
Temperature Range
-40℃ to 85℃
-40℃ to 85℃
Package
8-Pin SOP (S08)
8-Pin PSOP (PS08)
BLOCK DIAGRAM
VCCA
6
VDDQ
5
VIN
7
270k
+
-
270k
PG
1
Power Good
2
GND
2003/03/28
Champion Microelectronic Corporation
-
4
+
VREF
8
VOUT
3
VFB
Page 2
CM8563
1.5A L
INEAR
B
US
T
ERMINATION
R
EGULATOR
APPLICATION CIRCUITS
U1
CM8563
VREF
PG
PG
VREF
VDDQ
VDDQ
VOUT
COUT
VOUT
VCCA
VCCA
VFB
VIN
CIN
GND
Application Circuit for Bus Termination
U1
CM8563
VREF
PG
PG
VREF
VDDQ
VDDQ
VOUT
VOUT
R1
COUT
VCCA
VCCA
VFB
R1
VIN
CIN
GND
Application Circuit for Adjustable Output Voltage
2003/03/28
Champion Microelectronic Corporation
Page 3
CM8563
1.5A L
INEAR
B
US
T
ERMINATION
R
EGULATOR
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the
device could be permanently damaged.
VIN, VCCA, VDDQ to GND ......................….……... –0.3V to 6V
Storage Temperature
…….............……..……. -65°C to 150°C
Lead Temperature (Soldering, 5 sec)……………….. 260°C
Thermal Resistance(
θ
JC
)….. ……….. .14°C/W (PSOP-8)
Thermal Resistance(
θ
JC
)….. ……… 15.7°C/W (SOP-8)
OPERATING RANGE
(Note 1)
Junction Temperature Range (Note 2) ……………….. 0°C to 125°C
VCCA to GND ……………………………………………... 2.2V to 5.5V
VIN to GND ……………………………………………... 2.2V to VCCA
(Unless otherwise stated, these specifications apply T
A
=25°C;
VCCA=VIN=+2.5V and VDDQ=+2.5V (Note 3))
maximum ratings are stress ratings only and functional device operation is not
implied.
CM8563
Min.
1.21
-15
-20
Typ.
1.235
0
0.5
-0.5
5
540
I
OUT
=0A
(Note 6)
250
400
Max.
1.26
15
20
ELECTRICAL CHARACTERISTICS
Symbol
V
REF
V
OS
½ΔV
LOAD
½
Z
VREF
Z
VDDQ
I
CCQ
Power Good (Note 7)
Parameter
VREF Voltage
VOUT Output Voltage Offset
Load Regulation
(Note 5)
VREF Output Impedance
VDDQ Output Impedance
Quiescent Current
Test Conditions
I
REFOUT
=0mA
I
OUT
=0A
(Note 4)
I
OUT
: 0A -> 1.5A
I
OUT
: 0A -> -1.5A
I
REF
= -5uA to +5uA
Unit
V
mV
%
%
kΩ
kΩ
μA
Note 1:
Operating range indicates conditions for which the device is intended to be functional, but does not guarantee specific
performance limits. For guaranteed specification and test conditions see Electrical Characteristics.
Note 2:
At elevated temperatures, devices must be derated based on the thermal resistance. The SO-8 package must be derated
atθ
JA
= 151℃/W junction to ambient with no heat sink.
Note 3:
Limits are 100% production tested at 25℃. Limits over the operating temperature range are guaranteed through
correlation using Statistical Quality Control methods.
Note 4:
VOS = VREF – VOUT
Note 5:
Load regulation is tested by using a 10ms current pulse and measuring VOUT.
Note 6:
Quiescent current defined as the current flow into VCCA.
Note 7:
PG function but LP2995 does not have it. PG will be high as VTT is larger than 90% VREF, and PG will change to low
as VTT is lower than 85% VREF.
PG also will be low as VTT is greater than 115% VREF, and PG will change to high as
VTT is lower than 110% VREF. It has both directions PG function.
2003/03/28
Champion Microelectronic Corporation
Page 4
CM8563
1.5A L
INEAR
B
US
T
ERMINATION
R
EGULATOR
FUNCTIONAL DESCRIPTION
The CM8563 is a linear bus termination regulator designed to
meet the JEDEC requirements of SSTL-2 and SSTL-3. The
CM8563 is capable of sinking and sourcing current at the
output VOUT, regulating the voltage to equal VDDQ/2. A
buffered reference voltage that also tracks VDDQ/2 is
generated on the VREF pin for providing a global reference to
to track the VREF voltage with a tight tolerance over the entire
current range while preventing shoot through on the output
stage.
The CM8563 integrates power MOSFETs that are capable of
source and sink 1.5A of current while maintaining excellent
voltage regulation. The output voltage can be regulated within
3% or less by using the external feedback. Separate voltage
supply inputs have been added to fit applications with various
power supplies for the databus and power buses.
VOUT
VOUT is the regulated output that is used to terminate the bus
resistors. It is capable of sinking and sourcing current while
regulating the output precisely to VDDQ/2. The CM8563 is
designed to handle peak transient currents of up to +/- 3A with a
fast transient response. The maximum continuous current is a
function of VIN. If a transient is expected to last above the
maximum continuous current rating for a significant amount of
time then the output capacitor should be sized large enough to
prevent an excessive voltage drop.
VFB
The purpose of the VFB pin is to provide improved remote load
regulation. In most motherboard applications the termination
resistors will connect to VOUT in a long plane. If the output
voltage was regulated only at the output of the CM8563, then
the long trace will cause a significant IR drop, resulting in a
The VFB pin can be used to improve this performance, by
connecting it to the middle of the bus. This will provide a better
distribution across the entire termination bus.
the DDR-SDRAM and Northbridge Chipset. VOUT is designed termination voltage lower at one end of the bus than the other.
VREF
VREF provides the buffered output of the internal reference
voltage VDDQ/2. This output should be used to provide the
reference voltage of Northbridge chipset and memory.
Pin Description
VCCA & VIN
VCCA and VIN are the input supply pins for the CM8563.
VCCA is used to supply all the internal control circuitry for the
two op-amps and the output stage of VREF. VIN is used
exclusively to provide the rail voltage for the output stage on
the power operational amplifier used to the 2.5V rail for
optimal performance. This eliminates the need for bypassing
the two supply pins separately.
VDDQ
VDDQ is the input that is used to create the internal reference
voltage for regulating VOUT and VREF. This voltage is
generated by two internal 270kΩ resistors. This guarantees
that VOUT and VREF will track VDDQ/2 precisely.
2003/03/28
Champion Microelectronic Corporation
Page 5
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