Freescale Semiconductor, Inc.
MPC5200/D
Rev. 2, 5/2004
MPC5200 Hardware
Specifications
Topic
Page
NOTE:
Freescale Semiconductor, Inc...
1
2
3
4
5
6
7
Overview ......................................1
Features .......................................1
Electrical and Thermal
Characteristics..............................5
Package Description ..................60
System Design Information ........69
Ordering Information ..................74
Document Revision History ........75
The information in this document is subject to
change. For the latest data on the MPC5200, visit
www.mobilegt.com and proceed to the MPC5200
Product Summary Page.
1
Overview
The MPC5200 integrates a high performance MPC603e series G2_LE core with a
rich set of peripheral functions focused on communications and systems
integration. The G2_LE core design is based on the PowerPC
®
core architecture.
MPC5200 incorporates an innovative BestComm I/O subsystem, which isolates
routine maintenance of peripheral functions from the embedded G2_LE core. The
MPC5200 contains a SDRAM/DDR Memory Controller, a flexible External Bus
Interface, PCI Controller, USB, ATA, Ethernet, six Programmable Serial Controllers
(PSC), I
2
C, SPI, CAN, J1850, Timers, and GPIOs.
2
•
Features
MPC603e series G2_LE core
—
—
—
—
—
—
•
—
—
—
—
—
•
Superscalar architecture
760 MIPS at 400 MHz (-40 to +85
o
C)
16 k Instruction cache, 16 k Data cache
Double precision FPU
Instruction and Data MMU
Standard and Critical interrupt capability
up to 132-MHz operation
SDRAM and DDR SDRAM support
256-MByte addressing range per CS, two CS available
32-bit data bus
Built-in initialization and refresh
Key features are shown below.
SDRAM / DDR Memory Interface
Flexible multi-function External Bus Interface
— Supports interfacing to ROM/Flash/SRAM memories or other memory
mapped devices
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Features
—
—
—
—
•
—
—
—
—
—
•
8 programmable Chip Selects
Non multiplexed data access using 8/16/32 bit databus with up to 26-bit address
Short or Long Burst capable
Multiplexed data access using 8/16/32 bit databus with up to 25-bit address
Version 2.2 PCI compatibility
PCI initiator and target operation
32-bit PCI Address/Data bus
33- and 66-MHz operation
PCI arbitration function
Peripheral Component Interconnect (PCI) Controller
ATA Controller
— Version 4 ATA compatible external interface—IDE Disk Drive connectivity
BestComm DMA subsystem
— Intelligent virtual DMA Controller
— Dedicated DMA channels to control peripheral reception and transmission
— Local memory (SRAM 16 kBytes)
Freescale Semiconductor, Inc...
•
•
6 Programmable Serial Controllers (PSC), configurable for the following:
—
—
—
—
UART or RS232 interface
CODEC interface for Soft Modem, Master/Slave CODEC Mode, I
2
S and AC97
Full duplex SPI mode
IrDA mode from 2400 bps to 4 Mbps
•
•
Fast Ethernet Controller (FEC)
— Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE 802.3 MII, 10 Mbps 7-wire interface
Universal Serial Bus Controller (USB)
— USB Revision 1.1 Host
— Open Host Controller Interface (OHCI)
— Integrated USB Hub, with two ports.
Two Inter-Integrated Circuit Interfaces (I
2
C)
Serial Peripheral Interface (SPI)
Dual CAN 2.0 A/B Controller (MSCAN)
— Motorola Scalable Controller Area Network (MSCAN) architecture
— Implementation of version 2.0A/B CAN protocol
— Standard and extended data frames
•
•
•
•
J1850 Byte Data Link Controller (BDLC)
— J1850 Class B data communication network interface compatible and ISO compatible for low
speed (<125 kbps) serial data communications in automotive applications.
— Supports 4X mode, 41.6 kbps
— In-frame response (IFR) types 0, 1, 2, and 3 supported
2
MPC5200 Hardware Specifications
MOTOROLA
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Features
•
Systems level features
— Interrupt Controller supports four external interrupt request lines and 47 internal interrupt
sources
— GPIO/Timer functions
– Up to 56 total GPIO pins (depending on functional multiplexing selections) that support a
variety of interrupt/WakeUp capabilities.
– Eight GPIO pins with timer capability supporting input capture, output compare, and pulse
width modulation (PWM) functions
—
—
—
—
—
Real-time Clock with one-second resolution
Systems Protection (watch dog timer, bus monitor)
Individual control of functional block clock sources
Power management: Nap, Doze, Sleep, Deep Sleep modes
Support of WakeUp from low power modes by different sources (GPIO, RTC, CAN)
Freescale Semiconductor, Inc...
•
Test/Debug features
— JTAG (IEEE 1149.1 test access port)
— Common On-chip Processor (COP) debug port
•
On-board PLL and clock generation
Figure 1
shows a simplified MPC5200 block diagram.
MOTOROLA
MPC5200 Hardware Specifications
3
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4
Features
SDRAM / DDR
Systems Interface Unit (SIU)
SDRAM / DDR
Memory Controller
Real-Time Clock
System Functions
Interrupt Controller
GPIO/Timers
Local Plus Controller
Local
Bus
PCI Bus Controller
BestComm DMA
SRAM 16K
ATA Host Controller
SPI
USB
2x
I
2
C
2x
MSCAN
2x
J1850
Ethernet
PSC
6x
603
G2_LE Core
JTAG / COP
Interface
MPC5200 Hardware Specifications
Reset / Clock
Generation
Figure 1 Simplified Block Diagram—MPC5200
Freescale Semiconductor, Inc.
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CommBus
MOTOROLA
Freescale Semiconductor, Inc.
Electrical and Thermal Characteristics
3
3.1
Electrical and Thermal Characteristics
DC Electrical Characteristics
3.1.1 Absolute Maximum Ratings
The tables in this section describe the MPC5200 DC Electrical characteristics.
Table 1
gives the absolute
maximum ratings.
Table 1 Absolute Maximum Ratings
1
Characteristic
Supply voltage - G2_LE core and peripheral logic
Symbol
VDD_CORE
VDD_IO,
VDD_MEM_IO
SYS_PLL_AVDD
CORE_PLL_AVDD
Vin
Vin
Vinos
Vinus
Tstg
Min
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–
–
–55
Max
1.8
3.6
2.1
2.1
VDD_IO + 0.3
VDD_MEM_IO
+ 0.3
1.0
1.0
150
Unit
V
V
V
V
V
V
V
V
o
C
SpecID
D1.1
D1.2
D1.3
D1.4
D1.5
D1.6
D1.7
D1.8
D1.9
Freescale Semiconductor, Inc...
Supply voltage - I/O buffers
Supply voltage - System APLL
Supply voltage - G2_LE APLL
Input voltage (VDD_IO)
Input voltage (VDD_MEM_IO)
Input voltage overshoot
Input voltage undershoot
Storage temperature range
1
Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses
beyond those listed may affect device reliability or cause permanent damage.
3.1.2 Recommended Operating Conditions
Table 2
gives the recommended operating conditions.
Table 2 Recommended Operating Conditions
Characteristic
Supply voltage - G2_LE core and periph-
eral logic
Supply voltage - standard I/O buffers
Supply voltage - memory I/O buffers
(SDR)
Supply voltage - memory I/O buffers
(DDR)
Supply voltage - System APLL
Supply voltage - G2_LE APLL
Input voltage - standard I/O buffers
Input voltage - memory I/O buffers (SDR)
Input voltage - memory I/O buffers (DDR)
Symbol
VDD_CORE
VDD_IO
VDD_MEM_IO
SDR
VDD_MEM_IO
DDR
SYS_PLL_AVDD
CORE_PLL_AVDD
Vin
Vin
SDR
Vin
DDR
Min
1
1.42
3.0
3.0
2.42
1.42
1.42
0
0
0
Max
1
1.58
3.6
3.6
2.63
1.58
1.58
VDD_IO
VDD_MEM_IO
SDR
VDD_MEM_IO
DDR
Unit
V
V
V
V
V
V
V
V
V
SpecID
D2.1
D2.2
D2.3
D2.4
D2.5
D2.6
D2.7
D2.8
D2.9
MOTOROLA
MPC5200 Hardware Specifications
5
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