Datasheet
Serial EEPROM series Standard EEPROM
I
2
C BUS EEPROM (2-Wire)
BR24G01-3A
●General
Description
BR24G01-3A is a serial EEPROM of I
2
C BUS interface method
●Features
All controls available by 2 ports of serial clock(SCL) and
serial data(SDA)
Other devices than EEPROM can be connected to the
same port, saving microcontroller port
1.6V to 5.5V single power source action most suitable
for battery use
1MHz action is possible (1.7V to 5.5V)
Up to 8 bytes in page write mode
Self-timed programming cycle
Low current consumption
Prevention of write mistake
Write (write protect) function added
Prevention of write mistake at low voltage
More than 1 million write cycles
More than 40 years data retention
Noise filter built in SCL / SDA terminal
Initial delivery state FFh
●Packages
W(Typ.) x D(Typ.)x H(Max.)
DIP-T8
9.30mm x 6.50mm x 7.10mm
TSSOP-B8J
3.00mm x 4.90mm x 1.10mm
SOP8
5.00mm x 6.20mm x 1.71mm
MSOP8
2.90mm x 4.00mm x 0.90mm
SOP-J8
4.90mm x 6.00mm x 1.65mm
VSON008X2030
2.00mm x 3.00mm x 0.60mm
TSSOP-B8
3.00mm x 6.40mm x 1.20mm
Figure 1.
●BR24G01-3A
Capacity
Bit Format
Type
BR24G01-3A
BR24G01F-3A
BR24G01FJ-3A
1Kbit
128×8
BR24G01FVT-3A
BR24G01FVJ-3A
BR24G01FVM-3A
BR24G01NUX-3A
1.6V to 5.5V
Power Source
Voltage
Package
DIP-T8
SOP8
SOP-J8
TSSOP-B8
TSSOP-B8J
MSOP8
VSON008X2030
○Product
structure：Silicon monolithic integrated circuit
.
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○This
product is not designed protection against radioactive rays
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TSZ02201-0R2R0G100580-1-2
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BR24G01-3A
●Absolute
Maximum Ratings (Ta=25℃)
Parameter
Supply voltage
Symbol
V
CC
Ratings
-0.3 to +6.5
450 (SOP8)
450 (SOP-J8)
330 (TSSOP-B8)
Power Dissipation
Pd
310 (TSSOP-B8J)
310 (MSOP8)
300 (VSON008X2030)
800 (DIP-T8)
Storage Temperature
Operation Temperature
Input Voltage /
Output Voltage
Junction Temperature
Electrostatic discharge
voltage
(human body model)
Tstg
Topr
‐
Tjmax
V
ESD
－65
to +150
－40
to +85
-0.3 to Vcc+1.0
150
-4000 to +4000
℃
℃
V
℃
V
mW
Unit
V
Remarks
Datasheet
When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.3mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.0mW to be reduced per 1℃.
When using at Ta=25℃ or higher 8.0mW to be reduced per 1℃.
The Max value of input voltage / output voltage is not over 6.5V.
When the pulse width is 50ns or less, the Min value of input voltage
/ output voltage is not under -0.8V.
Junction temperature at the storage condition
●Memory
Cell Characteristics (Ta=25℃, Vcc=1.6V to 5.5V)
Limits
Parameter
Min.
Typ.
*1
1,000,000
－
Write cycles
*1
40
－
Data retention
*1Not 100% TESTED
Max
－
－
Unit
Times
Years
●Recommended
Operating Ratings
Parameter
Symbol
Supply voltage
Vcc
Input voltage
V
IN
Ratings
1.6 to 5.5
0 to Vcc
Unit
V
●DC
Characteristics (Unless otherwise specified, Ta=-40 to +85℃, Vcc =1.6 to 5.5V)
Limits
Parameter
Symbol
Unit
Min.
Typ.
Max.
Input High Voltage1
Input Low Voltage1
Input High Voltage2
Input Low Voltage2
Output Low Voltage1
Output Low Voltage2
Input Leakage Current
Output Leakage Current
Supply Current (Write)
Supply Current (Read)
Standby Current
VIH1
VIL1
VIH2
VIL2
VOL1
VOL2
ILI
ILO
ICC1
ICC2
ISB
0.7Vcc
－0.3
*1
0.8Vcc
－0.3
*1
－
－
－1
－1
－
-
－
－
－
－
－
－
－
－
－
－
-
－
Vcc+1.0
0.3Vcc
Vcc+1.0
0.2Vcc
0.4
0.2
1
1
2.0
mA
2.0
2.0
μA
V
V
V
V
V
V
μA
μA
Conditions
1.7V≦Vcc≦5.5V
1.7V≦Vcc≦5.5V
1.6V≦Vcc＜1.7V
1.6V≦Vcc＜1.7V
IOL=3.0mA, 2.5V≦Vcc≦5.5V (SDA)
I
OL
=0.7mA, 1.6V≦Vcc＜2.5V (SDA)
VIN=0 to Vcc
VOUT=0 to Vcc (SDA)
Vcc=5.5V, fSCL=1MHz, tWR=5ms,
Byte write, Page write
Vcc=5.5V, fSCL=1MHz
Random read, current read,
sequential read
Vcc=5.5V, SDA, SCL=Vcc
A0, A1, A2=GND,WP=GND
*1 When the pulse width is 50ns or less, it is -0.8V.
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BR24G01-3A
●AC
Characteristics (Unless otherwise specified, Ta=－40 to +85℃)
Parameter
Clock Frequency
Data Clock “HIGH“ Period
Data Clock “LOW“ Period
SDA, SCL (INPUT) Rise Time
*1
SDA, SCL (INPUT) Fall Time
*1
SDA (OUTPUT) Fall Time
*1
Start Condition Hold Time
Start Condition Setup Time
Input Data Hold Time
Input Data Setup Time
Output Data Delay Time
Output Data Hold Time
Stop Condition Setup Time
Bus Free Time
Write Cycle Time
Noise Spike Width (SDA, SCL)
WP Hold Time
WP Setup Time
WP High Period
*1 Not 100% tested
Datasheet
Symbol
fSCL
tHIGH
tLOW
tR
tF1
tF2
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tDH
tSU:STO
tBUF
tWR
tI
tHD:WP
tSU:WP
tHIGH:WP
Limits
(1.6V≦Vcc＜1.7V)
Min.
Typ.
Max.
-
0.6
1.2
-
-
-
0.6
0.6
0
100
0.1
0.1
0.6
1.2
-
-
1.0
0.1
1.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
-
-
1
1
0.12
-
-
-
-
0.9
-
-
-
5
0.05
-
-
-
Limits
(1.7V≦Vcc≦5.5V)
Min.
Typ.
Max.
－
0.3
0.5
－
－
－
0.25
0.20
0
50
0.05
0.05
0.25
0.5
－
－
1.0
0.1
1.0
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
1000
－
－
0.12
0.12
0.12
－
－
－
－
0.45
－
－
－
5
0.05
－
－
－
Unit
kHz
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
ms
µs
µs
µs
µs
●AC
Characteristics Condition
Parameter
Load Capacitance
SDA, SCL (INPUT) Rise Time
SDA, SCL (INPUT) Fall Time
Input Data Level
Input/Output Data Timing Reference Level
Symbol
CL
tR
tF1
VIL1/VIH1
-
Condition
100
20
20
0.2Vcc/0.8Vcc
0.3Vcc/0.7Vcc
Unit
pF
ns
ns
V
V
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BR24G01-3A
●Serial
Input / Output timing
tR
SCL
70%
30%
70% 70%
30%
Datasheet
tF1
tHIGH
70%
30%
70%
30%
tHD:STA
70%
70%
30%
70%
tLOW
tSU:DAT
tHD:DAT
70%
30%
SDA
(入力)
(INPUT)
SDA
(出力)
(OUTPUT)
tBUF
tPD
70%
30%
tDH
70%
30%
30%
○Input
read at the rise edge of SCL
○Data
output in sync with the fall of SCL
tF2
Figure 2-(a). Serial input / output timing
70%
70%
70%
tSU:STA
70%
30%
tHD:STA
tSU:STO
30%
START CONDITION
STOP CONDITION
Figure 2-(b). Start-stop bit timing
D0
write data
(n-th address)
ACK
70%
70%
tWR
STOP CONDITION
START CONDITION
Figure 2-(c). Write cycle timing
70%
DATA(1)
D1
D0
ACK
DATA(n)
ACK
70%
tWR
30%
30%
tSU:WP
tHD:WP
STOP CONDITION
Figure 2-(d). WP timing at write execution
DATA(1)
D1
D0
ACK
DATA(n)
ACK
tHIGH:WP
70%
70%
70%
tWR
Figure 2-(e). WP timing at write cancel
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BR24G01-3A
●Block
Diagram
A0 1
1Kbit
EEPROM
array
8bit
Datasheet
8
Vcc
A1 2
Address
decoder
7bit
Word
address register
Data
register
7
WP
START
STOP
A2 3
Control circuit
ACK
6
SCL
GND 4
High voltage
generating circuit
Power source
voltage detection
5
SDA
Figure 3. Block diagram
●Pin
Configuration
1
2
BR24G01-3A
A2
GND
●Pin
Descriptions
Terminal
Name
A0
A1
A2
GND
SDA
SCL
WP
Vcc
Input/
Output
Input
Input
Input
－
Input/
output
Input
Input
－
Function
Slave address setting*
Slave address setting*
Slave address setting*
Reference voltage of all input / output, 0V
Serial data input serial data output
Serial clock input
Write protect terminal
Connect the power source.
3
4
6 SCL
5 SDA
8 Vcc
7 WP
A0
A1
*A0, A1 and A2 are not allowed to use as open.
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FPGA/CPLD
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