DATA BULLETIN
MX839
Features
x
4 input intelligent 10 bit A/D monitoring
subsystem
4 High and 4 Low Comparators
External IRQ Generator
Free Running Operation
x
Three 8/10 bit DACs
x
Two Variable Attenuators
x
Selectable A/D Clock Frequencies
x
Full Control via 4-wire Serial Interface
x
Low Power 3.0 Operation
Digitally Controlled
Analog I/O Processor
PRELIMINARY INFORMATION
Applications
x
PCS, Cellular, LMR, Wireless
Transceivers, and General Purpose
x
Monitor and Control:
RSSI, Battery State, Temperature,
VSWR, and Error Voltages
x
Digital Trim and Calibration:
VCOs, TCXO, Power Output, Bias,
Current, IF Gain, Deviation,
Modulation Depth, and Baseband
Gain
RECEIVER
RSSI
VSWR
RF TRANSMITTER
RADIO BATTERY STATE
BATTERY
SYSTEM
4 x 10 bit Free Run A/D
4 x Hi Comparator
4 x Low Comparator
IRQ on Compare
Clock Osc
& Dividers
3x
8/10 bit
DAC
TX POWER
REF. OFFSET TRIM
VCO TRIM
MX839
2x
Variable
Attenuator
MOD 1 OUT
MOD 2 OUT
MOD 1 IN
MOD 2 IN
TRANSMITTER
MODULATOR
TEMPERATURE
C-BUS Interface
& Control Logic
µC
C-BUS SERIAL BUS 0 : 3
The MX839 is a low power CMOS µC peripheral device which provides digitally controlled calibration, trimming, and
monitoring functions for PCS, cellular, LMR, wireless transceivers, and general purpose applications.
Featuring a four input intelligent 10 bit A/D monitoring subsystem, an interrupt generator, three 8/10 bit DACs, and two
variable attenuator functions, the MX839 automatically monitors, produces, and trims up to nine analog signals via a
simple four wire serial control bus. The free running A/D intelligent monitoring subsystem includes independent high and
low limit comparators for each of four analog input signals which can be configured to generate external µC interrupts.
The MX839’s high level of integration reduces end product parts count, component size, and software complexity. MX839
digital trimming functions also reduce manufacturing costs by eliminating manual trimming operations.
Featuring an operating range of 3.0V to 5.5V the MX839 is available in 24-pin SSOP (MX839DS), 24-pin SOIC
(MX839DW), and 24-pin PDIP (MX839P) packages.
© 1998 MXxCOM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480164.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
Digitally Controlled Analog I/O Processor
2
MX839 PRELIMINARY INFORMATION
CONTENTS
Section
Page
1 Block Diagram ................................................................................................................................ 3
2 Signal List ....................................................................................................................................... 4
3 External Components..................................................................................................................... 5
4 General Description ....................................................................................................................... 6
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Variable Attenuators............................................................................................................................... 6
Digital to Analog Converters................................................................................................................... 6
Analog to Digital Converter and A/D Clock Generator ........................................................................... 6
Magnitude Comparators and Interrupt Request ..................................................................................... 7
Software Description .............................................................................................................................. 7
Read Only Registers (8-Bit and 16-Bit) .................................................................................................. 9
Write Only Register Description ............................................................................................................. 9
Read Only Register Description ............................................................................................................ 13
5 Application ..................................................................................................................................... 13
5.1
C-Bus Clock .......................................................................................................................................... 13
6 Performance Specification ........................................................................................................... 14
6.1
6.2
Electrical Performance .......................................................................................................................... 14
Packaging.............................................................................................................................................. 19
MXxCOM, Inc. reserves the right to change specifications at any time and without notice.
© 1998 MXxCOM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480164.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
Digitally Controlled Analog I/O Processor
3
MX839 PRELIMINARY INFORMATION
1 Block Diagram
MOD1 IN
MUTE1
0 to 12dB x 0.4dB Steps
MOD1OUT
MUTE2
MOD2 IN
0 to 16dB x 0.2dB Steps
MOD2OUT
HIGH COMPARATOR
A/D REG1
LOW COMPARATOR
A/DIN1
A/DIN2
A/DIN3
A/DIN4
4:1
MUX
A/D
10
bit
HIGH COMPARATOR
A/D REG2
LOW COMPARATOR
HIGH COMPARATOR
A/D REG3
LOW COMPARATOR
HIGH COMPARATOR
A/D REG4
LOW COMPARATOR
DACOUT1
DAC1
8/10 bit
DACOUT2
DAC2
8/10 bit
DACOUT3
DAC3
8/10 bit
1:4
MUX
ADC COMP IRQ
REPLY DATA
COMMAND DATA
CS
SERIAL CLOCK
XTAL/CLOCK
XTAL
4-wire
SERIAL INTERFACE
AND LOGIC
CONTROL
CLOCK
OSCILLATOR
AND DIVIDERS
AV
DD
V
SS
V
BIAS
DV
DD
DV
DD
AV
DD
Figure 1: Block Diagram
© 1998 MXxCOM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480164.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
Digitally Controlled Analog I/O Processor
4
MX839 PRELIMINARY INFORMATION
2 Signal List
Pin No.
1
2
3
4
Name
XTAL
XTAL/CLOCK
SERIAL CLOCK
COMMAND DATA
Type
output
input
input
input
Description
The output of the on-chip oscillator inverter.
The input to the on-chip oscillator inverter, for external Xtal circuit or clock.
The 'C-BUS' serial clock input. This clock, produced by the µC, is used for
transfer timing of commands and data to and from the device. See Figure 5.
The 'C-BUS' serial data input from the µC. Data is loaded into this device in
8-bit bytes, MSB (B7) first, and LSB (B0) last, synchronized to the SERIAL
CLOCK. See Figure 5.
The 'C-BUS' serial data output to the µC. The transmission of REPLY DATA
bytes is synchronized to the SERIAL CLOCK under the control of the CS
input.
This tri-state output is held at high impedance when not sending data to the
µC. See Figure 5.
The 'C-BUS' data loading control function. This input is provided by the µC.
Data transfer sequences are initiated, completed or aborted by the CS signal.
See Figure 5.
This output indicates an interrupt condition to the µC by going to a logic '0'.
This is a 'wire-ORable' output, enabling the connection of up to 8 peripherals
to 1 interrupt port on the µC. This pin has a low impedance pulldown to logic
'0' when active and a high-impedance when inactive. An external pullup
resistor is required.
The conditions that cause interrupts are indicated in the IRQ FLAG register
and are effective if not disabled.
Analog to digital converter input 1 (A/D1)
Analog to digital converter input 2 (A/D2)
Analog to digital converter input 3 (A/D3)
Analog to digital converter input 4 (A/D4)
Negative supply (ground) for both analog and digital supplies.
An analog bias line for the internal circuitry, held at AV
DD
/2. This pin must be
bypassed by a capacitor mounted close to the device pins.
No internal connection. Do not make any connection to this pin.
output
output
output
power
input
input
output
output
power
Digital to analog converter No. 1 output (DAC1)
Digital to analog converter No. 2 output (DAC2)
Digital to analog converter No. 3 output (DAC3)
No internal connection. Do not make any connection to this pin.
Positive analog supply. Analog levels and voltages are dependent upon this
supply. This pin should be bypassed to V
SS
by a capacitor.
Input to MOD1 variable attenuator.
Input to MOD2 variable attenuator.
Output of MOD1 variable attenuator.
Output of MOD2 variable attenuator.
Positive digital supply. Digital levels and voltages are dependent upon this
supply. This pin should be bypassed to V
SS
by a capacitor.
5
REPLY DATA
output
6
CS
input
7
IRQ
output
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A/DIN1
A/DIN2
A/DIN3
A/DIN4
V
SS
V
BIAS
N/C
DACOUT1
DACOUT2
DACOUT3
N/C
AV
DD
MOD1 IN
MOD2 IN
MOD1
MOD2
DV
DD
input
input
input
input
power
output
© 1998 MXxCOM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480164.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
Digitally Controlled Analog I/O Processor
5
MX839 PRELIMINARY INFORMATION
3 External Components
XTAL
X1
R1
XTAL/CLOCK
C2
C1
C-BUS
INTERFACE
XTAL
XTAL/CLOCK
SERIAL CLOCK
COMMAND DATA
REPLY DATA
CS
IRQ
ADCIN1
ADCIN2
ADCIN3
ADCIN4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
MX839
R2
24
23
22
21
20
19
18
17
16
15
14
13
DV
DD
MOD2 OUT
MOD1 OUT
MOD2 IN
MOD1 IN
AV
DD
N/C
DACOUT3
DACOUT2
DACOUT1
N/C
V
BIAS
DV
DD
C5
R3
AV
DD
C4
C6
DV
DD
C3
Figure 2: Recommended External Components
R1
R2
R3
C1
C2
C3
Note 1
1M:
22k:
10:
22pF
22pF
0.1µF
±5%
±10%
±10%
±20%
±20%
±20%
X1
Note 2, 3
±100ppm
C4
C5
C6
Note 1
Note 1
0.1µF
0.1µF
10.0µF
±20%
±20%
±20%
Table 1: Recommended External Components
Notes:
1. These values should be determined in regard to the amount of supply filtering required for D/A outputs.
2. If an external clock is to be used, then it should be connected to Pin 2 and the components C1, C2, R1, and X1
omitted. The ADC clock frequency is derived from the crystal or external clock by means of internal programmable
dividers. See Section 6 for details of crystal or external clock frequency range.
3. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of
V
DD
, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator design
assistance, consult your crystal manufacturer.
© 1998 MXxCOM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480164.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
