July 2004
AS91L1006BU
6-Port JTAG Gateway
Description
The AS91L1006BU is a one to 6-port
JTAG gateway. It partitions a single JTAG chain
into six separate chains. These separate chains
can be optionally configured to operate as a single
chain.
The AS91L1006BU device is used to
provide enhanced capabilities to the standard
IEEE1149.1. It enables the IEEE1149.1 interface
to be used in a true Multi-Drop environment without
any additional signals. This Multi-Drop capability
enables the standard IEEE1149.1 interface to be
used not just for stand alone PCB (Printed Circuit
Board) testing, but also for complete system
testing including all PCBs within a system back
plane environment.
The AS91L1006BU provides the capability
of partitioning the PCB, into multiple smaller
IEEE1149.1 scan chains totally under software
control. Partitioning the IEEE1149.1 chains on the
PCB has several benefits which include easier
fault diagnostics capabilities as a fault on one of
the IEEE1149.1 Local Scan Ports (LSPs) does
not render the PCB untestable, faster flash
programming on the PCBs, and removal of
IEEE1149.1 signal loading issues.
All of the protocols required for
addressing the AS91L1006BU device via the
Multi-Drop capability and the protocols for
configuring which of the six IEEE1149.1 LSPs on
the AS91L1006BU are to be used, is handled via
3
rd
party ATPG tools from vendors like Asset-
Intertech and JTAG Technologies. In a Multi-Drop
environment it is also possible to perform
interconnect tests between multiple PCBs within a
system thus extending the interconnect tests to
the back plane itself.
Key Features
Device Multi-Drop addressable via the IEEE
1149.1 protocol
Support for 6 local scan chains addressable via
the IEEE 1149.1 interface
Support for Pass-Through™
Support for the IEEE 1149.1 USERCODE
instruction
Support for Status instruction enabling non-
intrusive monitoring of the system card
Local Scan Port (LSP) enable signal provides the
ability to use non IEEE 1149.1 compliant devices
that require JTAG enable signal
Provides the ability to initiate Self-Test on a
remote PCB via a standard IEEE 1149.1
command
Support for JTAG Technologies AutoWR™
feature
Pinout and feature set compatible (complete
second source) with the Firecron JTS06BU
device
Available in a 100-pin LQFP or a 100-pin
FPBGA lead free package
Device Block Diagram
P a s s T h r o u g h E n a b le
P r im a r y 1 1 4 9 . 1
J T A G In te rfa c e
LSP1
S ta tu s D a ta
LSP2
U s e rc o d e
D a ta
1 1 4 9 . 1 T A P C o n t r o lle r
and
B o u n d a r y R e g is t e r S e le c t io n L o g ic
D e v ic e
a d d re s s
P a s s T h ro u g h
L o g ic & L o c a l
S c a n P o rt
C o n n e c t io n /
C o n f ig
lo g ic
LSP3
LSP4
D e v ic e
S e le c t io n
L o g ic
L o c a l S c a n P o rt
P a r k /U n -p a rk
S y n c L o g ic
LSP5
LSP6
Figure 1 - AS91L1006BU Device Block Diagram
Alliance Semiconductor
2575 Augustine Drive
•
Santa Clara, CA 95054
•
T: 408-855-4900
•
F: 408-855-4999
•
www.alsc.com
July 2004
AS91L1006BU
AS91L1006BU Gateway Functional Description
The basic structure of the AS91L1006BU
device is shown in Figure-1. The core of the device
is the 16-state IEEE1149.1 TAP controller state
machine. All accesses to the internal registers of
the AS91L1006BU device are controlled via this
state machine during normal operation as per the
IEEE1149.1 standard. The address selection logic
enables the AS91L1006BU to operate in a Multi-
Drop environment within system backplane.
The address selection logic compares the
scanned address to the slot address value
presented on the I/O of the AS91L1006BU device.
The LSP park/unpark logic provides control
through instructions scanned in under the
IEEE1149.1 protocol, to select, which LSP will be
placed into the active, scan chain. The pass-
through and LSP connection logic selects the
signal paths for the LSP IEEE1149.1 signals. The
device also supports a Pass-Through mode which
enables the primary IEEE1149.1 signals to be
routed to any of the LSPs. This signal routing is
selectable via I/O pins on the AS91L1006BU
device.
Figure-2 shows the device selection state
machine. The AS91L1006BU will perform an
address compare on the slot address presented
at its I/O and the value scanned in via the
IEEE1149.1. If the value matches then the
AS91L1006BU becomes selected and is ready for
normal access via IEEE1149.1 commands. If the
address does not match then the device will
proceed to the unselected mode, where it will
remain until the AS91L1006BU is issued a
GOTOWAIT instruction or a reset occurs via
TRST or the LSP_RESET pin.
Selected Single
Device
Device
Unselected
Parked-RTI
Wait for
Selection
Parked-TLR
Parked-
PauseDR
UnParked
Select Group
of Devices
Select All
Devices
Parked-
PauseIR
Figure 2 - AS91L1006BU
Selection Logic State machine
Figure 3 - The LSP
Park/Unpark State Machine
The LSP Park/Unpark State Machine controls the insertion of the LSPs into the current active scan
chain. The ability to park the LSP in certain IEEE1149.1 states, enable the AS91L1006BU to perform
several functions including backplane interconnect testing and IC BIST.
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Alliance Semiconductor
2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved.
2
July 2004
AS91L1006BU
AS91L1006BU Detailed Mode of Operation
Addressing the AS91L1006BU device
After a Test-Logic-Reset or power-up, the
AS91L1006BU device will be in its Wait-for-
Selection state with its TDO pin tri-stated, thus
avoiding contention in a Multi-Drop environment.
The AS91L1006BU device will respond to a
device-select sequence for a particular address
that is auto generated by third party test tools with
respect to the address that is pre-loaded on its
S(5..0). Once this sequence has been completed,
the AS91L1006BU device will respond to normal
IEEE 1149.1 instructions. Note that addresses 60-
63 have been reserved and the AS91L1006BU
device will not respond if the user selects these
addresses.
The AS91L1006BU device should be in
the Wait-for-Selection mode, which can be
entered into by issuing an asynchronous reset
(through the deassertion of TRST) or by issuing a
synchronous reset (through the assertion of TMS
for five cycles of TCK). After the device has been
selected, it can be issued a GOTOWAIT
instruction.
The internal IEEE1149.1 state machine of
the AS91L1006BU device is taken to the Shift-IR
phase and the required Device-ID is shifted into
the Instruction register. As the IEEE1149.1 state
machine passes through the Update-IR phase,
the address is matched to the value on the S(5-0)
pins on the AS91L1006BU device; if the values
match, then the AS91L1006BU device is selected
and is ready to receive any normal IEEE1149.1
command.
S(5-0) value
< 3A hex or 60
decimal
Table 1 - AS91L1006BU
IR (7 – 0) value
XXVVVVVV
Device Selection Table
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Alliance Semiconductor
2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved.
3
July 2004
AS91L1006BU
Table 2 - AS91L1006BU Multi Cast Group
Selection Table
Selection
Mode
Single
Address
Mode
Binary
Function
Address
XX000000 to Single AS91L1006BU
XX111010
selected the TDO of
the device will be
active
All accessible
AS91L1006BU
devices are selected
for operation. TDO on
all devices will be in
HighZ
Access all
AS91L1006BU
devices that have
been placed in GRP0
by their MCGR
contents
Access all
AS91L1006BU
devices that have
been placed in GRP1
by their MCGR
contents
Access all
AS91L1006BU
devices that have
been placed in GRP2
by their MCGR
contents
Access all
AS91L1006BU
devices that have
been placed in GRP3
by their MCGR
contents
Table 3 - AS91L1006BU Device
Register Description
Register
Name
Instruction
Register
Description
AS91L1006BU device
addressing and instruction-
decode
IEEE Std. 1149.1 required
register
IEEE Std. 1149.1 required
register
IEEE Std. 1149.1 required
register
IEEE Std. 1149.1 optional
register
IEEE Std. 1149.1 optional
register
AS91L1006BU device non
intrusive 8-bit register pre load
able from the I/O pins
AS91L1006BU device specific
single bit register for initiating
self testing on a PCB
AS91L1006BU device local-port
configuration and control bits
AS91L1006BU device Auto
Write feature enable register
AS91L1006BU device Async
reset register for the LSPs
Broad
XX111011
Cast Mode
Multi-Cast XX111100
Group 0
Multi-Cast XX111101
Group 1
Boundary-
Scan
Register
Bypass
Register
Device
Identification
Register
User Code
Register
Status
Register
Self Test
Register
Mode
Register
Auto Write
Register
LSP Async
Reset
Register
Multi-Cast XX111110
Group 2
Multi-Cast XX111111
Group 3
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Alliance Semiconductor
2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved.
4
July 2004
AS91L1006BU
Hex Op-
Code
FF
00
81
AA
E7
C5
84
C6
C3
8E
03
88
97
98
99
Binary Op- Data Register
Code
11111111 Bypass Register
00000000
10000001
10101010
11100111
11000101
10000100
11000110
11000011
10001110
00000011
10001000
10010111
10011000
10011001
Boundary-Scan Register
Boundary-Scan Register
Device Identification Register
Device Identification Register
Device Identification Register
Device Identification Register
Device Identification Register
Device Identification Register
Mode Register
Multi-Cast Group Register.
Device Identification Register
User Programmable 32 Bit Identification Register
Auto Write Feature Enable Register
Single bit low pulse, used to initiate function on PCB
(SELF_TEST pin)
User programmable status byte (USER_STATUS_DATA
pins)
Toggles LSP TRST while maintaining the AS91L1006BU
in the selected state.
Device Identification Register
Instructions
BYPASS
EXTEST
SAMPLE/PRELOAD
IDCODE
UNPARK
PARKTLR
PARKRTI
PARKPAUSE
GOTOWAIT*
MODESELECT
MCGRSELECT
SOFTRESET
USERCODE
AUTOWR
STEST_PCB
STATUS_BYTE
LSP_ASYNC_RESET
9A
9B
10011010
10011011
Other Undefined
TBD
TBD
Table 4 - AS91L1006BU Device Instruction Register OpCodes
Note: All instructions act on a single selected AS91L1006BU device only.
* This instruction causes the AS91L1006BU to become unselected and revert to the Wait-for-
Selection state.
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2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved.
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