ARM720T
(Rev 3)
Technical Reference Manual
ARM DDI 0192A
ARM720T
Technical Reference Manual
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
Release information
Change history
Date
September 2000
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http://www.arm.com
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Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
Contents
ARM720T Technical Reference Manual
List of Tables
............................................................................................................vii
List of Figures
............................................................................................................ix
Preface
About this document .....................................................................................................xii
Further reading..............................................................................................................xv
Feedback .....................................................................................................................xvi
Chapter 1
Introduction
1.1
1.2
1.3
About the ARM720T ..................................................................................... 1-2
Coprocessors ................................................................................................ 1-4
About the instruction set ............................................................................... 1-5
Chapter 2
Programmer’s Model
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Processor operating states ........................................................................... 2-2
Memory formats ............................................................................................ 2-3
Instruction length........................................................................................... 2-5
Data types ..................................................................................................... 2-6
Operating modes .......................................................................................... 2-7
Registers ....................................................................................................... 2-8
The program status registers ...................................................................... 2-13
ARM DDI 0192A
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
iii
2.8
2.9
2.10
2.11
Exceptions .................................................................................................. 2-16
Relocation of low virtual addresses by the FCSE PID................................ 2-22
Reset .......................................................................................................... 2-23
Implementation-defined behavior of instructions ........................................ 2-24
Chapter 3
Configuration
3.1
3.2
3.3
About configuration....................................................................................... 3-2
Internal coprocessor instructions.................................................................. 3-3
Registers ...................................................................................................... 3-4
Chapter 4
Instruction and Data Cache
4.1
4.2
4.3
4.4
About the instruction and data cache ........................................................... 4-2
IDC validity ................................................................................................... 4-4
IDC enable, disable, and reset ..................................................................... 4-5
IDC disable for secure applications .............................................................. 4-6
Chapter 5
Write Buffer
5.1
5.2
About the write buffer ................................................................................... 5-2
Write buffer operation ................................................................................... 5-3
Chapter 6
Memory Management Unit
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
About the MMU............................................................................................. 6-2
MMU program accessible registers .............................................................. 6-4
Address translation process ......................................................................... 6-5
Level 1 descriptor ......................................................................................... 6-7
Page table descriptor.................................................................................... 6-8
Section descriptor......................................................................................... 6-9
Translating section references ................................................................... 6-11
Level 2 descriptor ....................................................................................... 6-12
Translating small page references ............................................................. 6-14
Translating large page references.............................................................. 6-16
MMU faults and CPU aborts....................................................................... 6-18
Fault address and fault status registers...................................................... 6-19
Domain access control ............................................................................... 6-21
Fault checking sequence............................................................................ 6-22
External aborts ........................................................................................... 6-25
Interaction of the MMU, IDC, and write buffer ............................................ 6-26
Chapter 7
Debug Interface
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
About the debug interface ............................................................................ 7-2
Debug systems............................................................................................. 7-4
Entering debug state .................................................................................... 7-7
Scan chains and JTAG interface .................................................................. 7-9
Reset .......................................................................................................... 7-11
Public instructions....................................................................................... 7-12
Test data registers...................................................................................... 7-16
ARM7TDM core clocks............................................................................... 7-23
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Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
7.9
7.10
7.11
7.12
7.13
Determining the core and system state....................................................... 7-25
The PC during debug.................................................................................. 7-30
Priorities and exceptions ............................................................................. 7-34
Scan interface timing .................................................................................. 7-35
Scan and debug signals used by the embedded trace logic....................... 7-42
Chapter 8
EmbeddedICE Logic
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
About EmbeddedICE Logic........................................................................... 8-2
The watchpoint registers............................................................................... 8-4
Programming breakpoints ............................................................................. 8-9
Programming watchpoints........................................................................... 8-11
The debug control register .......................................................................... 8-13
Debug status register .................................................................................. 8-15
Coupling breakpoints and watchpoints ....................................................... 8-17
Debug communications channel ................................................................. 8-19
Chapter 9
Bus Clocking
9.1
9.2
9.3
About the ARM720T bus interface................................................................ 9-2
Fastbus extension......................................................................................... 9-3
Standard mode ............................................................................................. 9-5
Chapter 10
AMBA Interface
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
About the AMBA interface........................................................................... 10-2
ASB bus interface signals ........................................................................... 10-3
Cycle types ................................................................................................. 10-4
Addressing signals ...................................................................................... 10-7
Memory request signals .............................................................................. 10-8
Data signal timing ....................................................................................... 10-9
Slave response signals ............................................................................. 10-10
Maximum sequential length ...................................................................... 10-12
Read-lock-write ......................................................................................... 10-13
Little-endian and big-endian operation...................................................... 10-14
Multi-master operation .............................................................................. 10-17
Bus master handover ................................................................................ 10-19
Default bus master.................................................................................... 10-21
Chapter 11
AMBA Test
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Slave operation, test mode ......................................................................... 11-2
ARM720T test mode ................................................................................... 11-3
ARM7TDM core test mode.......................................................................... 11-5
RAM test mode ........................................................................................... 11-6
TAG test mode............................................................................................ 11-8
MMU test mode......................................................................................... 11-10
Test register mapping ............................................................................... 11-11
Chapter 12
Trace Interface Port
12.1
About the ETM ............................................................................................ 12-2
ARM DDI 0192A
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
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