AN731
Vishay Siliconix
Simple Solution for Dynamically Programming the
Output Voltage of DC-DC Converters
INTRODUCTION
Figure 1 shows a typical dc-to-dc converter configuration. As in
many PWM controllers, the non-inverting input of the voltage
feedback error amplifier is internally connected to the
reference voltage, V
r
. The output voltage of the converter is set
by a resistor divider network R1 and R2. This configuration
enables a fixed output voltage that is equal to or greater than
the reference voltage. But in many power conversion designs,
it is useful to vary the output to a value lower than the reference
voltage and to dynamically adjust the output voltage. The
op-amp circuit shown in Figure 3 gives designers a simple way
to do this. Scaling the output voltage with respect to a control
voltage V
C
is totally flexible. This application note describes
how to use this simple solution and provides a step-by-step
design procedure to assist designers in calculating the specific
parameters required by their circuits.
DESIGN REQUIREMENT
Reference voltage, V
r
Control voltage: V
C
= V
C1
to V
C2
Output voltage: V
O
= V
O1
at V
C
= V
C1
, V
O
= V
O2
at V
C
= V
C2
,
and V
O
is linear for any value of V
C
in its range.
These design requirements are shown in Figure 2. The output
voltage is a linear function with respect to the control voltage.
The function crosses two end points A = (V
C1
, V
O1
) and B =
(V
C2
, V
O2
).
V
IN
Power Stage
V
OUT
V
O
(V)
B (V
C2
, V
O2
)
R1
PWM
FB
–
+
V
r
R2
EA
PWM Controller
A (V
C1
, V
O1
)
V
C
(V)
FIGURE 1.
Typical DC/DC Converter Configuration
FIGURE 2.
Output Voltage vs Control Voltage Requirement
V
IN
Power Stage
V
OUT
R1
PWM
FB
–
+
A
V
r
R2
B
V
X
LM358
–
+
V
r2
Op-Amp Circuit
R3
EA
PWM Controller
R4
V
C
FIGURE 3.
Op-Amp Circuit Offers Programmable Output Function
Document Number: 71128
28-Jan-00
www.vishay.com
S
FaxBack 408-970-5600
1
AN731
Vishay Siliconix
CIRCUIT ANALYSIS
In a closed-loop power supply, node A will servo to attain a
voltage equal to V
R
. Node B will servo to attain a voltage equal
to V
r2
. Assuming an ideal op-amp and using Kirchkorf’s current
law at node A and B, we have:
(Vo
*
Vr)
(Vr
*
Vx)
+
R1
R2
and
(Vx
*
Vr2)
(Vr2
*
Vc)
+
R3
R4
(1)
³
b
+
Vo2
*
aVc2
+
1
)
1 Vr
*
1
)
a Vr2
m1
m1
(7)
Equate (4) and (5) and solve for m1
m1
+
Vr
*
Vr2
Vo2
)
a(Vr2
*
Vc2)
*
Vr
(8)
Note:
m1
+
R2
R1
(9)
Let:
M1
+
R2
R1
and
M2
+
R3
R4
(2)
Since m1 is the ratio of 2 real resistors, it must be a positive
number. Furthermore, m1 should not be too small or too large
to have realistic resistor values for R1 and R2. There are two
valid scenarios:
1. Vr – Vr2 > 0
2. Vr – Vr2 < 0
and
and
Vo2 + a(Vr2 – Vc2)–Vr > 0 or,
Vo2 + a(Vr2 – Vc2)–Vr < 0
Solve for V
X
,
Vx
+
(1
)
m1)Vr
*
m1Vo
and
Vx
+
(1
)
m2)Vr2
*
m2Vc
(3)
Both of these present a restricted range of values for V
r2
to give
a meaningful value of m1. Once V
r2
is chosen correctly, m1
and the rest of the parameter values can be determined.
Equate the above two equations and solve for V
O
:
Vo
+
1
)
1 Vr
*
1
)
m2 Vr2
)
m2 Vc
+
b
)
aVc
m1
m1
m1
(4)
DESIGN PROCEDURE AND EXAMPLE
Given:
A = (V
C1
, V
O1
) = (0.2 V, 0.4 V), B = (V
C2
, V
O2
) = (2.7 V, 3.4 V)
V
r
= 1.3 V, R1 = 22.1 kW. Also, 1 V < V
X
< 3 V.
Where:
a
+
m2
m1
and
b
+
1
)
1 Vr
*
1
)
m2 Vr2
m1
m1
(5)
Calculate the slope, a:
a
+
Vo2
*
Vo1
+
3.4
*
0.4
+
1.2
2.7
*
0.2
Vc2
*
Vc1
(10)
Determine V
r2
:
So, V
O
is a linear function with respect to V
C
. The function has
slope a and y intercept b.
A curve-fitting technique is used to force the equation (4) to
follow the requirement. This is done in two steps:
Matching the slope:
a
+
Vo2
*
Vo1
+
m2
m1
Vc2
*
Vc1
(6)
Choose a sensible value of V
r2
to satisfy either (1) or (2) above.
Since it is easier to derive a value for V
r2
that is smaller than V
r
(by using a simple resistor voltage divider), scenario (1) is used
here.
Vr–Vr2
u
0
å
Vr2
t
Vr
+
1.3 V
and,
Vo2
)
a(Vr2–Vc2)–Vr
u
0
å
Vr2
u
Vr–Vo2
)
Vc2
+
1.3 V–3.4 V
)
2.7
+
0.95V
a
1.2
(11)
Matching one point: Pick point B
→V
O2
= b + aV
C2
www.vishay.com
S
FaxBack 408-970-5600
2
Document Number: 71128
28-Jan-00
AN731
Vishay Siliconix
To limit the common mode range of V
X
, the following equations
can be used:
1. To keep V
X
equal or greater than a minimum value, V
Xm
=
1 V:
Vr2
w
Vxm(Vo2–Vr–aVc2)
)
aVc2Vr
+
Vo2
)
a(Vr–Vxm)–Vr
1.3
+
1.249
The final result: V
O
= aV
C
+ b = 1.223 x V
C
+ 0.1389
EXPERIMENTAL RESULTS
A circuit was built and tested (see Figure 5). The result is
tabulated in Table 1 and plotted in Figure 4:
1(3.4–1.3–1.2 2.7)
)
1.2 2.7
3.4
)
1.2(1.3–1)–1.3
(12)
2. To keep V
X
equal or less than a maximum value, V
Xm
=
3 V:
Vr2
w
VxM(Vo2–Vr–aVc2)
)
aVc1Vr
+
Vo2
)
a(Vr–VxM–Vc2
)
Vc1)–Vr
TABLE 1
V
X
V
C
Measured
1.43
1.42
1.38
1.32
1.25
1.19
1.11
1.05
1.02
1.00
0.99
0.96
V
O
Calculated
0.26
0.38
0.63
1.12
1.61
2.10
2.58
3.07
3.32
3.44
3.56
3.81
Measured
0.32
0.42
0.68
1.16
1.66
2.12
2.68
3.11
3.33
3.46
3.58
3.78
Required
0.40
0.64
1.12
1.60
2.08
2.56
3.04
3.28
3.40
2(3.4–1.3–1.2 2.7)
)
1.2 0.2 1.3
+
1.13 V
3.4
)
1.2(1.3–2–2.7
)
0.2)–1.3
(13)
0.1
0.2
0.4
So, V
r2
can be any value between 1.249 V and 1.3 V. Choose
V
r2
= 1.25 V.
Calculate m1 and then R2:
m1
+
Vr–Vr2
+
Vo2
)
a(Vr2–Vc2)–Vr
1.3–1.25
+
0.139
3.4
)
1.2(1.25–2.7)–1.3
m1
+
R2
å
R2
+
m1R1
+
0.139
R1
22.1 k
+
3.07 kW
0.8
1.2
1.6
2.0
2.4
2.6
(14)
2.7
2.8
3.0
Choose R2 = 3.01 kW as a practical value
4.0
Calculate R3 and R4:
a
+
m2
+
R3
å
R3
+
am1R4
m1
m1R4
(15)
Output Voltage–V (V)
O
3.5
3.0
2.5
2.0
1.5
V
X
Measured
1.0
0.5
V
O
Choose R4, then calculate R3. The value of R4 should be large
enough such that the current going through it will not be so
large as to cause excessive power dissipation under extreme
conditions. On the other hand, R4 should be small enough that
its current will not be overly sensitive to noise and op-amp bias
current.
If R4 is set at 22.1k, then R3 = 3.68 k, and we can choose R3
= 3.60 k as a practical value.
Express V
O
as a function of V
C
, using practical values of R’s:
a
+
m2
+
R1R3
+
22.1kx3.68k
+
1.223
m1
R2R4
3.01kx22.1k
b
+
1
)
1 Vr– 1
)
a Vr2
+
m1
m1
R1
)
1 Vr– R1
)
a Vr2
R2
R2
0
0
0.5
1.0
1.5
2.0
2.5
3.0
Control Voltage—V
C
(v)
FIGURE 4.
(16)
b
+
22.1k
)
1 1.3– 22.1k
)
1.223 1.25
+
0.1389
3.01k
3.01k
Document Number: 71128
28-Jan-00
The measured values are very much in agreement with the
calculated and required values. A negligible error results from
the difference between an ideal op-amp and the actual circuit
with its finite offset voltage and bias current.
www.vishay.com
S
FaxBack 408-970-5600
3
AN731
Vishay Siliconix
DYNAMIC RESPONSE PERFORMANCE
Figures 7 and 8 show the dynamic response of the output
voltage with different dynamic control voltages. The V
O
response and settling time depend on the following factors:
1. the bandwidth of the converter control loop: the larger the
bandwidth, the faster V
O
response time
2. the large signal response slew rate of the converter: the
faster the slew rate, the faster the response
3. the slew rate of the converter control loop error amplifier
4. the bandwidth of the difference amplifier.
The bandwidth of the converter control loop is the most
important parameter. The maximum attainable bandwidth of a
converter control loop is 1/(2*pi) times the switching frequency.
For a converter switching at 100 kHz, the control bandwidth is
limited to 16 kHz. Vishay Siliconix high-frequency switching
regulators (including the Si9165, Si9169, and Si9170) offer
switching frequencies up to 2 MHz and have a theoretical
bandwidth limit of 318 kHz. Thus they would be good
candidates for this kind of application. Figure 5 shows a
complete example of a dc-to-dc converter using the Si9165
controller IC and the op-amp circuit. The output voltage can be
programmed from 0.4 V to 3.4 V with a control voltage from
The bandwidth of the difference amplifier requires the
difference amplifier to have its unity gain bandwidth a decade
or more larger than the control loop bandwidth.
0.2 V to 2.7 V. Figure 6 shows a similar example using the
Si9166 controller.
The signal response slew rate of the converter dictates how
fast the converter can slew its output voltage up or down given
an infinitely large control loop bandwidth. The converter slew
rate depends on the converter output averaging LC filter. The
smaller the LC, the faster the slew rate.
With respect to the slew rate of the converter control loop error
amplifier, most of the converter control loop is figured as an
integrator. The error amplifier often drives a fairly large
integrator capacitor. The slew rate of the op-amp should be
sized adequately.
CONCLUSION
A simple op-amp circuit is used to program the output voltage
of a typical dc-to-dc converter. The circuit offers flexible voltage
scaling using a linear control voltage. The control voltage can
be hard-wired for fixed-voltage operation. When used together
with a wide bandwidth dc-to-dc converter, the circuit offers a
simple solution for controlling the output voltage dynamically.
www.vishay.com
S
FaxBack 408-970-5600
4
Document Number: 71128
28-Jan-00
AN731
Vishay Siliconix
P1
1
V
IN
2.7 – 6 V
C8
0.1
mF
C7
10
mF
JP1
Enable
Converter
Disable
V
DD
JP2
PWM
–PSM
1
U1
1
2
3
4
5
6
NC
SD
PWM/PSM
V
IN/OUT
V
IN/OUT
V
IN/OUT
SYNC
GND
V
REF
FB
COIL
COIL
MODE
PGND
PGND
V
S
V
O
V
DD
R
OSC
COMP
20
19
18
17
16
15
14
13
12
11
R6
3.9 kW
C1
100 pF
C6
1 nF
R3
25 kW
C2
0.1
mF
R2
3.01 kW
1%
V
DD
1.5
mH
D1
MBR0520T1
R4*
50
W
C4
220 pF
R1
22.1 kW
1%
R5
1 kW
0.4 – 3.4 V
600 mA
Adjustable
C3
10
mF
P4
1
PGND
P3
V
OUT
L1
P2
1
SYNC
+1.3 V
7
8
9
10
GND
C5
0.1
mF
Si9165
P5
V
A
0.2 – 2.7 V
R8, 22.1 kW
1
R9, 390
W
V
IN
R11
3.60 kW
U2A
-
+
1
V
X
LM358D
R10
10 kW
8
6
5
U2B
-
+
4
LM358D
7
NC
C10
0.1
mF
JP1: –SD to V
IN
for converter enable mode;
–SD to PGND for shutdown mode.
JP2: PWM/–PSM to V
IN
for PWM mode;
PWM/–PSM to PGND for PSM mode.
NOTE: V
IN
must be > V
OUT
+0.6 V for output regulation
* = Optional
FIGURE 5.
Schematic of Design Example, Using Si9165 Converter
Document Number: 71128
28-Jan-00
www.vishay.com
S
FaxBack 408-970-5600
5
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
