AN231E04 Datasheet Rev 1.0
3
rd
Generation
Dynamically Reconfigurable dpASP
This device is RoHS compliant
www.anadigm.com
DS231000-U001d
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Disclaimer
Anadigm reserves the right to make any changes without further notice to any products herein. Anadigm makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
Anadigm assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including with out limitation consequential or incidental damages. "Typical" parameters can and do
vary in different applications. All operating parameters, including "Typicals" must be validated for each customer
application by customer's technical experts. Anadigm does not in this document convey any license under its patent
rights nor the rights of others. Anadigm software and associated products cannot be used except strictly in accordance
with an Anadigm software license. The terms of the appropriate Anadigm software license shall prevail over the above
terms to the extent of any inconsistency.
© Anadigm
®
, Inc. 2007
All Rights Reserved.
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AN231E04 Datasheet – Dynamically Reconfigurable dpASP
PRODUCT AND ARCHITECTURE OVERVIEW
The AN231E04 device is an “Analog Signal Processor”; ideally
suited to signal conditioning, filtering, gain, rectification, summing,
subtracting, multiplying, etc.
The device also accommodates nonlinear functions such as
sensor response linearization and arbitrary waveform synthesis.
The AN231E04 device consists of a 2x2 matrix of fully
Configurable
Analog
Blocks
(CABs),
surrounded
by
programmable interconnect resources and analog input/output
cells with active elements. On chip clock generator block controls
multiple non-overlapping clock domains generated from an
external stable clock source. Internal band-gap reference
generator is used to create temperature compensated reference
voltage levels. The inclusion of an 8x256 bit look-up table
enables waveform synthesis and several non-linear functions.
Configuration data is stored in an on-chip SRAM configuration
memory. An SPI like interface is provided for simple serial load of
configuration data from a microprocessor or DSP. This memory is
shadowed allowing a different circuit configuration to be loaded
as a background task without disrupting the current circuit
functionality.
The AN231E04 device features seven configurable input/output
structures each can be used as input or output, 4 of the 7 have
integrated differential amplifiers. There is also a single chopper
stabilized amplifier that can be used by 3 of the 7 output cells.
Figure 1: Architectural overview of the AN231E04 device
Circuit design is enabled using Anadigmdesigner2 software, a
high level block diagram based circuitry entry tool. Circuit
functions are represented as CAMs (Configurable Analog
Modules) these are configurable block which map onto portions
of CABs. The software and a development board facilite instant
prototyping of any circuit captured in the tool.
With dynamic reconfigurability, the functionality of the
AN231E04 can be reconfigured in-system by the designer or
on-the-fly by a microprocessor. A single AN231E04 can thus
be programmed to implement multiple analog functions
and/or to adapt on-the-fly to your circuit requirements.
PRODUCT FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
Dynamic reconfiguration
Seven configurable I/O cells, two dedicated output cells
Fully differential architecture
I/O buffering with single ended to differential conversion
Low input offset through chopper stabilized amplifiers
256 Byte Look-Up Table (LUT) for linearization and
arbitrary signal generation
Typical Signal Bandwidth: DC-2MHz (Bandwidth is CAM
dependent)
Signal to Noise Ratio:
o
Broadband 90dB
o
Narrowband (audio) 120dB
Total Harmonic Distortion (THD): 100dB
User controlled Compensated low DC offset <250µV
DC Offset via chopper stabilized architecture <50uV
Package: 44-pin QFN (7x7x0.9mm)
o
Lead pitch 0.5mm
Supply voltage: 3.3V
APPLICATIONS
•
•
•
•
•
•
•
•
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Analog Signal Processing
RFID IF (Baseband Filtering)
Real-time software control of analog system peripherals
Intelligent sensors
Adaptive filtering and control
Adaptive DSP front-end
Adaptive industrial control and automation
Self-calibrating systems
Compensation for aging of system components
Dynamic recalibration of remote systems
Ultra-low frequency signal conditioning
Custom analog signal processing
ORDERING CODES
AN231E04-e2-QFNTY
AN231E04-e2-QFNTR
dpASP Tray (260 /tray, 2600/box)
dpASP Tape & Reel (1000 /reel, 4000/box)
AN231E04-e2-QFNSP
AN231K04-DVLP3
dpASP Sample Pack
AN231E04 Development Kit
[For
more detailed information on the features of the AN231E04 device, please refer to the AN131E04/AN231E04 User Manual]
DS231000-U001d
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1
1.1
AN231E04 Datasheet – Dynamically Reconfigurable dpASP
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
AVDD
BVDD
DVDD
Min
-0.5
-0.5
Typ
-
Max
3.6 V
0.5
Unit
V
V
Comment
AVSS, BVSS and DVSS all held
to 0.0 V
Ideally all supplies should be at
the same voltage
(Theoretical values based on
Tj=125deg.C)
Still air, No heatsink, 44 pads and
exposed die pad soldered to PCB
θja
= 22.5°C/W. VDD = 3.3V
Maximum power dissipation all
resources used, (see section
1.5.13 for more detail).
Parameter
DC Power Supplies
a
xVDD to yVDD Offset
Package Power Dissipation,
Pmax 25°C
Pmax 85°C
-
-
4.5
1.8
W
AN231E04 max power
dissipation
Input Voltage
Ambient Operating
Temperature
Storage Temperature
a
dpASPmax
Vinmax
Top
Tstg
-
VSS-0.5
-40
-40
-
-
-
0.25
VDD+0.5
85
125
W
V
°C
°C
Absolute Maximum DC Power Supply Rating - The failure mode is non-catastrophic for VDD of up to 5 volts, but will cause
reduced operating life time. The additional stress caused by higher local electric fields within the CMOS circuitry may induce
metal migration, oxide leakage and other time/quality related issues.
1.2
Recommended Operating Conditions
Symbol
AVDD
BVDD
DVDD
Min
3.0
Typ
3.3
Max
3.6
Unit
V
Comment
AVSS, BVSS and DVSS all held
to 0 V
Conditional on the circuit which is
being driven. This limit is defined
as maximum signal amplitude
through input Sample and hold
cell which results in >-80dB
THD+N using a 1KHz test signal.
VMR is 1.5 volts above AVSS
Assume a package
θja=22.5°C/W
Parameter
DC Power Supplies
Analog Input Voltage.
Vina
VMR
-1.375
-
VMR
+1.375
V
Digital Input Voltage
Junction Temp
b
b
Vind
Tj
0
-40
-
-
DVDD
125
V
°C
To calculate the junction temperature (Tj) you must first empirically determine the current draw (total Idd) for the design. The
programmable nature of this device means this can vary by orders of magnitude between different circuit designs. Once the current
consumption is established then the following formula can be used; Tj = Ta + Idd x VDD x 22.5 °C/W, where Ta is the ambient
temperature. Worst case
θja
= 22.5 °C/W assumes no air flow and no additional heatsink, 44 pads and the exposed die pad soldered
to PCB.
1.3
General Digital I/O Characteristics (VDD = 3.3v +/- 10%, -40 to 85 deg.C)
Symbol
Vih
Vil
Vol
Voh
Iil
Cmax
Rmin
Fmax
CLKduty
Min
0
70
0
80
-
-
50
-
45
Typ
-
-
-
-
-
-
-
16
-
Max
30
100
20
100
+/-1
10
-
40
55
Unit
-
-
-
-
µA
pF
Kohm
MHz
%
Each pins has a specific load
driving capability, detailed in
sections 1.4 and 1.5
Divide down to <4 MHz prior to
use as a CAB clock
All clocks
Comment
% of DVDD
% of DVDD
% of DVDD
% of DVDD
Some pins have active pull
up/down, please see below.
Parameter
Input Voltage Low
Input Voltage High
Output Voltage Low
Output Voltage High
Input Leakage Current
Max. Capacitive Load
Min. Resistive Load
ACLK Frequency
Clock Duty Cycle
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AN231E04 Datasheet – Dynamically Reconfigurable dpASP
1.4
Digital I/O Characteristics (VDD = 3.3v +/-10%, -40 to 85 deg.C unless commented)
1.4.1
Pins ACLK, SCLK, RESETb, CS1b, CS2b, SI, MODE (standard CMOS inputs)
Symbol
Vil
Vih
Min
0
70
Typ
-
-
Max
30
100
Unit
%
%
Comment
% of DVDD
% of DVDD
Parameter
Input Voltage Low
Input Voltage High
1.4.2
Pin SO, (standard CMOS output)
Symbol
Vol
Voh
Cmax
Rmin
Min
VSS
3.28
-
5
Typ
-
-
-
-
Max
VSS
VDD
100
-
Unit
mV
V
pF
Kohm
Comment
Load 10pF//50Kohm to VSS
Load 10pF//50Kohm to VSS
VDD = 3.3 V.
Maximum load 100 pF // 5 Kohm
at up to 5MHz.
Maximum load 100 pF // 5 Kohm
at up to 5MHz.
Pin shorted to VDD
Current should be limited
externally so that it does not
exceed 3mA
Pin shorted to VSS.
Current should be limited
externally so that it does not
exceed 3mA
Parameter
Output Voltage Low
Output Voltage High
Max. Capacitive Load
Min. Resistive Load
Current Sink
Isnkmax
60
100
135
mA
Current Source
Isrcmax
50
80
110
mA
1.4.3
Digital functions of mixed signal Pins IO1, IO2, IO3, IO4, IO5, IO6, IO7,
These pins can be configured by the user to be standard CMOS input or outputs.
I/O cells 5, 6 and 7 the pin pairs can be connected to and used individually.
I/O cells 1 through 4 provide pin pairs for differential (complimentary) digital connections
.
Parameter
Input Voltage Low
Input Voltage High
Output Voltage Low
Output Voltage High
Max. Capacitive Load
Min. Resistive Load
Symbol
Vil
Vih
Vol
Voh
Cmax
Rmin
Min
0
70
VSS
3.25
-
50
Typ
-
-
-
-
Max
30
100
VSS
VDD
50
-
Unit
%
%
mV
V
pF
Kohm
Current Sink
Isnkmax
15
30
40
mA
Current Source
Isrcmax
15
25
35
mA
Comment
% of DVDD
% of DVDD
Pin load = 20pF//10K to VSS
Pin load = 20pF//10K to VSS
VDD = 3.3 V.
Maximum load 20 pF // 10 Kohm
at up to 4MHz signal
Maximum load 20 pF // 10 Kohm
at up to 4MHz signal
Pin shorted to VDD.
Current should be limited
externally so that it does not
exceed 3mA
Pin shorted to VSS.
Current should be limited
externally so that it does not
exceed 3mA.
DS231000-U001d
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