AN221E04 Datasheet
Dynamically Reconfigurable FPAA
With Enhanced I/O
www.anadigm.com
DS030100-U006a
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Disclaimer
Anadigm reserves the right to make any changes without further notice to any products herein. Anadigm makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
Anadigm assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including with out limitation consequential or incidental damages. "Typical" parameters can and
do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer
application by customer's technical experts. Anadigm does not in this document convey any license under its patent
rights nor the rights of others. Anadigm software and associated products cannot be used except strictly in
accordance with an Anadigm software license. The terms of the appropriate Anadigm software license shall prevail
over the above terms to the extent of any inconsistency.
© Anadigm
®
Ltd. 2003
© Anadigm
®
, Inc. 2003
All Rights Reserved.
DS030100-U006a
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AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
PRODUCT AND ARCHITECTURE OVERVIEW
The AN221E04 device consists of a 2x2 matrix of fully
Configurable Analog Blocks (CABs), surrounded by a fabric of
programmable interconnect resources. Configuration data is
stored in an on-chip SRAM configuration memory. Compared
with the first-generation FPAAs, the Anadigmvortex architecture
provides a significantly improved signal-to-noise ratio as well as
higher bandwidth. These devices also accommodate nonlinear
functions such as sensor response linearization and arbitrary
waveform synthesis.
The AN221E04 device features an advanced input/output
structure that allows the FPAA to be programmed with up to six
outputs – or triple the number provided by the ANx20E04
devices. The AN221E04 devices have four configurable I/O cells
and two dedicated output cells. For I/O-intensive applications, this
means a single FPAA can now be used to process multiple
channels of analog signals where two or more such devices were
previously needed.
In addition, the AN221E04 devices allow designers to implement
an integrated 8-bit analog-to-digital converter on the FPAA,
eliminating the potential need for an external converter. Using this
new device, designers can route the digital output of the A/D
converter off-chip using one of the dedicated output cells.
Figure 1: Architectural overview of the AN221E04 device
With dynamic reconfigurability, the functionality of the
AN221E04 can be reconfigured in-system by the designer or
on-the-fly by a microprocessor. A single AN221E04 can thus
be programmed to implement multiple analog functions
and/or to adapt on-the-fly to maintain precision operation
despite system degradation and aging.
PRODUCT FEATURES
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Dynamic reconfiguration
Four configurable I/O cells, two dedicated output cells
8-bit SAR analog–to–digital converter
Fully differential architecture
Fully differential I/O buffering with options for single ended
to differential conversion
Low input offset through chopper stabilized amplifiers
256 Byte Look-Up Table (LUT) for linearization and
arbitrary signal generation
4:1 Input multiplexer
Typical Signal Bandwidth: DC-2MHz (Bandwidth is CAM
dependent)
Signal to Noise Ratio:
o
Broadband 80dB
o
Narrowband (audio) 100dB
Total Harmonic Distortion (THD): 80dB
DC offset <100µV
Package: 44-pin QFP (10x10x2mm)
o
Lead pitch 0.8mm
Supply voltage: 5V
Dynamically reconfigurable FPAA
Sample Pack
Dynamically reconfigurable FPAA
Tray (96 pcs)
Dynamically reconfigurable FPAA
Tape & Reel (1000 pcs)
AN221E04 Evaluation Kit
AN221E04 Development Kit
APPLICATIONS
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Real-time software control of analog system peripherals
Intelligent sensors
Adaptive filtering and control
Adaptive DSP front-end
Adaptive industrial control and automation
Self-calibrating systems
Compensation for aging of system components
Dynamic recalibration of remote systems
Ultra-low frequency signal conditioning
Custom analog signal processing
ORDERING CODES
AN221E04-QFPSP
AN221E04-QFPTY
AN221E04-QFPTR
AN221D04-EVAL
AN221D04-DEVLP
[For
more detailed information on the features of the AN221E04 device,
please refer to the AN121E04/AN221E04 User Manual]
DS030100-U006a
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AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
DC Power Supplies
xVDD to xVDD Offset
Package Power Dissipation
Analog and Digital Input Voltage
Ambient Operating Temperature
Storage Temperature
a
Symbol
AVDD(2)
BVDD
DVDD
Pmax 25°C
Pmax 85°C
Vinmax
Top
Tstg
Min
-0.5
-0.5
-
Vss-0.5
-40
-65
Typ
-
Max
5.5 V
0.5
Unit
V
V
W
V
°C
°C
Comment
AVSS, BVSS, DVSS and SVSS all
held to 0.0 V
a
Ideally all supplies should be at the
same voltage
Still air, No heatsink, 4 layer board,
44 pins.
θja
= 55°C/W
-
-
-
1.8
0.73
Vdd+0.5
85
150
Absolute Maximum DC Power Supply Rating - The failure mode is non-catastrophic for Vdd of up to 7 volts, but will cause reduced
operating life time. The additional stress caused by higher local electric fields within the CMOS circuitry may induce metal migration,
oxide leakage and other time/quality related issues.
Recommended Operating Conditions
Parameter
DC Power Supplies
Symbol
AVDD(2)
BVDD
DVDD
Vina
Vind
Tj
Min
4.75
VMR-1.9
0
-40
Typ
5.00
-
-
-
Max
5.25
VMR+1.9
DVDD
125
Unit
V
V
V
°C
Comment
AVSS, BVSS, DVSS and SVSS all
held to 0 V
VMR is 2.0 volts above AVSS
Assume a package
θja
= 55°C/W
b
Analog Input Voltage.
Digital Input Voltage
Junction Temp
b
In order to calculate the junction temperature you must first empirically determine the current draw (total Idd) for the design. Once the
current consumption established then the following formula can be used; Tj = Ta + Idd x Vdd x 55 °C/W, where Ta is the ambient
temperature. The worst case
θja
of 55 °C/W assumes no air flow and no additional heatsink of any type.
General Digital I/O Characteristics (Vdd = 5v +/- 10%, -40 to 85 deg.C)
Parameter
Input Voltage Low
Input Voltage High
Output Voltage Low
Output Voltage High
Input Leakage Current
Input Leakage Current
Max. Capacitive Load
Min. Resistive Load
DCLK Frequency
ACLK Frequency
Clock Duty Cycle
Symbol
Vih
Vil
Vol
Voh
Iil
Iil
Cmax
Rmin
Fmax
Fmax
-
Min
0
70
0
80
-
-
-
10
-
-
45
Typ
-
-
-
-
-
±12.0
-
-
-
-
-
Max
30
100
20
100
±1.0
-
10
-
40
40
55
Unit
-
-
-
-
µA
µA
pF
Kohm
MHz
MHz
%
Comment
% of DVDD
% of DVDD
% of DVDD
% of DVDD
All pins except DCLK
DCLK if a crystal is connected and
the on-chip oscillator is used
The maximum load for a digital
output is 10 pF // 10 Kohm
The maximum load for a digital
output is 10 pF // 10 Kohm
For MODE = 1, Max DCLK is
16 MHz
Divide down to <8 MHz prior to use
as a CAB clock
All clocks
DS030100-U006a
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AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
Detailed Digital I/O Interface Characteristics: Vdd = 5.0volts
LCCb
Parameter
Output Voltage Low
Output Voltage High
Max. Capacitive Load
Min. Resistive Load
Current Sink
Current Source
Symbol
Vol
Voh
Cmax
Rmin
Isnkmax
Isrcmax
Min
Vss
4.5
-
50
-
-
Typ
-
-
-
-
-
-
Max
150
Vdd
20
-
15
4
Unit
mV
V
pF
Kohm
mA
mA
Comment
Load 20pF//50Kohm to Vss
Load 20pF//50Kohm to Vss
Maximum load 20 pF // 50 Kohm
Maximum load 20 pF // 50 Kohm
LCCb pin shorted to Vdd
LCCb pin shorted to Vss
CFGFLG, ACTIVATE
Parameter
Input Voltage Low
Input Voltage High
Output Voltage Low
Output Voltage High
Output Voltage Low
Vol
Output Voltage High
Voh
Max. Capacitive Load
Min. Resistive Load
Current Sink
Current Source
External Resistive Pullup
Cmax
Rmin
Isnkmax
Isrcmax
Rpullupext
4.5
-
50
-
-
5
-
-
-
-
-
7.5
Vdd
50
-
2.5
200
10
V
pF
Kohm
mA
µA
Kohm
Vss
-
200
mV
Symbol
Vil
Vih
Vol
Voh
Min
0
70
Vss
4.5
Typ
Max
30
100
Unit
%
%
mV
V
Comment
% of DVDD
% of DVDD
Pin load =
Internal pullup + 20pF//50K to Vss
Pin load =
Internal pullup + 20pF//50K to Vss
Pin Load =
External 5K ohm pullup +
20pF//50K to Vss
Pin Load =
External 5Kohm pullup +
20pF//50K to Vss
Maximum load 50 pF // 50 Kohm
Maximum load 50 pF // 50 Kohm
Pin shorted to Vdd
Pin shorted to Vss
Use only if internal pullup is
deselected
-
-
85
Vdd
ERRb
Parameter
Input Voltage Low
Input Voltage High
Output Voltage Low
Output Voltage High
Max. Capacitive Load
Min. Resistive Load
Current Sink
Current Source
External Resistive Pullup
Symbol
Vil
Vih
Vol
Voh
Cmax
Rmin
Isnkmax
Isrcmax
Rpullupext
Min
0
70
Vss
4.9
-
50
-
-
10
Typ
-
-
-
-
-
-
10
Max
30
100
50
Vdd
50
-
10
0
10
Unit
%
%
mV
V
pF
Kohm
mA
µA
Kohm
Comment
% of DVDD
% of DVDD
Maximum load 50 pF // 50 Kohm
Maximum load 50 pF // 50 Kohm
DCLK,Mode,DIN,EXECUTE,PORb,CS1b,CS2b
Parameter
Input Voltage Low
Input Voltage High
Symbol
Vil
Vih
Min
0
70
Typ
-
-
Max
30
100
Unit
%
%
Comment
% of DVDD
% of DVDD
DS030100-U006a
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